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A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC
(IEEE Computer Soc, 2008)
This paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation free algorithm that causes a high level reduction on memory requirement, hardware resources ...
Low complexity inter-mode selection for H.264
(IEEE, 2006)
The coding efficiency of the H.264/AVC standard enables the transmission of high quality video over bandwidth limited networks. Due to the use of multiple Macroblock (MB) partitions, the Motion estimation module has extremely ...