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Toplam kayıt 3, listelenen: 1-3
Analysis and design of low-cost bit-serial architectures for motion estimation in H.264/AVC
(Springer, 2013-05)
Variable block-size motion estimation (VBSME) process occupies a major part of computation of an H.264 encoder, which is usually accelerated by bit-parallel hardware architectures with large I/O bit width to meet real-time ...
Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264
(World Scientific Publishing Company, 2010-12)
The sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. ...
A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC
(IEEE Computer Soc, 2008)
This paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation free algorithm that causes a high level reduction on memory requirement, hardware resources ...