Ara
Toplam kayıt 4, listelenen: 1-4
Analysis and design of low-cost bit-serial architectures for motion estimation in H.264/AVC
(Springer, 2013-05)
Variable block-size motion estimation (VBSME) process occupies a major part of computation of an H.264 encoder, which is usually accelerated by bit-parallel hardware architectures with large I/O bit width to meet real-time ...
Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264
(World Scientific Publishing Company, 2010-12)
The sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. ...
A survey of algorithms and architectures for H.264 sub-pixel motion estimation
(World Scientific, 2012-05)
This paper reviews recent state-of-the-art H. 264 sub-pixel motion estimation (SME) algorithms and architectures. First, H.264 SME is analyzed and the impact of its functionalities on coding performance is investigated. ...
A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264
(IEEE, 2009)
Bit-serial architectures offer a number of attractive features over their bit-parallel counterparts such as smaller area cost, lower density interconnection, a reduced number of pins, higher clock frequency, simpler routing ...