METAMUTATOR:
ITS REALIZATIONS AND ITS APPLICATIONS
ELHAM MİNAYİ
IŞIK UNIVERSITY
2019
ELHAM MİNAYİ Ph. D. Thesis 2019
METAMUTATOR:
ITS REALIZATIONS AND ITS APPLICATIONS
ELHAM MİNAYİ
B.S. Electrical and Electronic Engineering, ISLAMIC AZAD UNIVERSITY
(IAU), Tehran, 2004
M.S. Electronics and Communication Engineering, DOĞUŞ UNIVERSITY
(DOU), 2014
Submitted to the Graduate School of Science and Engineering
in partial fulfillment of the requirements for the degree of
Doctor of Philosophy
in
Electronic Engineering
IŞIK UNIVERSITY
2019
IŞIK UNIVERSITY
GRADUATE SCHOOL OF SCIENCE AND ENGINEERING
METAMUTATOR: ITS REALIZATIONS AND ITS APPLICATIONS
ELHAM MİNAYİ
APPROVED BY:
Prof. İ. Cem Göknar Işık University
(Thesis Supervisor)
Prof. Vedat Tavşanoğlu Işık University
Prof. Serdar Özoğuz Istanbul Technical University
Prof. Dr. Hasan Fehmi Ateş Istanbul Medipol University
Assist. Prof. Merih Yıldız Doğuş University
APPROVAL DATE: ..../..../....
METAMUTATOR:
ITS REALIZATIONS AND ITS APPLICATIONS
Abstract
Mutators became very popular after 1971, when Leon Chua realized the memris-
tor, his postulated fourth circuit element, using them. The reason for the popu-
larity of mutators, which are easily realizable 2-port devices, lies in the fact that
they render possible the simulation/emulation of, hence experimentation with,
postulated non-existing (not off the shelf available) elements like memstors.1
On the other hand, in the literature when simulating/emulating elements with 2-
ports, many 4-port “generalized mutator-like” realizations that nobody has been
able to identify are being used. These underlying 4-ports, and their ability to
act as a mutator when two of the ports are properly terminated, have been thus
named metamutator.
In this thesis, in addition to introducing some of metamutator realizations, newly
designed metamutator circuits with one or two active devices are introduced.
Also, a new active device, with only twelve transistors, named Additive and Dif-
ferential IC (AD-IC), is proposed with its layout and use in metamutator circuit
design. In addition, many 1-port and 2-port circuit realizations using metamu-
tators have been introduced. 1-port applications are memstor simulation/em-
ulation, floating and/or grounded impedance scaling which comprise inductance
simulation, capacitance multiplication, oscillators and Frequency Dependent Neg-
ative Resistor (FDNR) simulation. 2- port applications cover Voltage Mode Mul-
tiple Input Single Output (VM-MISO) and Current Mode Single Input Multiple
Output (CM-SIMO) universal filters and implementations of transconductance
and transimpedance amplifiers. Also, two different applications of AD-IC: AD-
IC based analog multiplier and AD-IC based full-wave rectifier are proposed in
the thesis.
Keywords: Mutator, memstor, memristor, metamutator, universal filter,
FDNR, analog multiplier, RC-oscillator, AD-IC
1Memstor is a generic name for memristor, memcapacitor, meminductor and memris-
tance, meminductance, memcapacitance respectively.
ii
METAMUTATOR:
GERÇEKLEMELERİ VE UYGULAMALARI
Özet
Leon Chua’nın 1971 yılında memristorları, onları kullanarak gerçeklemesinden
sonra mutatorlar ilgi odağı olmaya başladılar. Mutatorların ilgi çekmelerinin ne-
deni piyasada bulunmayan yeni ortaya atılmış memristor gibi, ya da bobin benzeri
entegre devre teknolojisi ile uyumlu olmayan elemanların mutator devreleri kul-
lanarak simüle/emüle edilebilmesidir.
Diğer yandan, literatürde 2-kapılılar ile elemanlar simüle/emüle edilirken, kişiler
farkına varmadan çoğu zaman genelleştirilmiş mutator benzeri bir 4-kapılı yapı
kullanmışlardır. Altta yatan bu gizli 4-kapılılar ve bunların iki kapıları uygun son-
landırıldığında diğer iki kapıdan mutator gibi davranmaları, metamutator adının
takılmasına neden olmuştur.
Bu tezde metamutatorun, farkına varılmayan gerçeklenmeleri ve yeni geliştirilmiş
bir veya iki aktif elemanlı devreleri verilmiş ve sadece on iki tranzistor kullanılarak
yeni tasarlanmış bir toplayıcı ve çıkarıcı entegre devresi ile (AD-IC) bu devre
tabanlı bir metamutator tanıtılmıştır.
Ayrıca metamutator kullanarak çeşitli 1-kapılı ve 2-kapılı gerçeklemeleri ile bun-
ların birçok farklı uygulamaları tanıtılmıştır. 1 kapılı devre gerçeklemeleri ile
yapılmış uygulamalara örnek olarak, endüktans simülatörü, kapasitans çarpım
devresi, frekansa bağlı negatif direnç, osilatörler ve yüzer veya topraklanmış
empedans dönüştürme uygulamaları tanıtılıp simülasyonları yapılmıştır. 2 kapılı
olarak yapılmış uygulamalara örnek olarak: transkondüktans ve transempedans
kuvvetlendiricileri, gerilim modlu çok girişli tek çıkışlı ve akım modlu tek girişli
çok çıkışlı evrensel süzgeçlerin uygulamaları yapılmıştır. Ayrıca, bu tezde AD-
IC tabanlı iki farklı uygulama da önerilmiştir. Birincisi AD-IC tabanlı analog
çarpma devresi, ikincisi AD-IC tabanlı tam dalga doğrultucu devresidir.
Anahtar kelimeler:mutator; memstor; memristor; metamutator; evrensel
filtre; FDNR; çarpma devresi; osilatör; AD-IC
iii
Acknowledgements iv
There are many people who helped to make my years at the graduate school
most valuable. First of all my special thanks goes to my thesis advisor Prof.
Dr. İ. Cem Göknar for his efforts, patience and guidance during this work and
also sincerely thanks to Prof. Dr. Vedat Tavşanoğlu, Prof. Dr. Serdar Özoğuz
and Asst. Prof. Merih Yıldız for their invaluable comments, their time and
their efforts for improving the thesis.
After that thanks to my dear husband Shahram who has encouraged me for
entering and helping for continuing this way by his constructive ideas during
this thesis.
Also I thank my lovely daughter Aylin, who with patience has endured staying
away from her mother.
And thanks my dear parents Homa and Reza and also my beloved brothers
Alireza and Hamidreza, who have supported and encouraged me in all stages
of life.
To
My husband Shahram
&
My parents Homa & Reza
Table of Contents
Abstract ii
Özet ii
Acknowledgements iii
List of Tables viii
List of Figures ix
List of Abbreviations xii
1 Introduction 1
1.1 Basic Circuit Elements and Memstors . . . . . . . . . . . . . . . . 1
1.2 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Generalized 4-Port Mutators: Metamutators . . . . . . . . . . . . 13
1.4 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2 Mutator Circuits and Memstor Simulations 19
2.1 Mutators for Mutating Nonlinear Circuit Elements to Memristor . 20
2.1.1 Mutators for Mutating Nonlinear Resistor to Memristor . . 20
2.1.2 Mutators for Mutating Nonlinear-Inductor to Memristor . 23
2.1.3 Mutators for Mutating Nonlinear-Capacitor to Memristor . 25
2.2 Mutators for Mutating Memristor to Other Memstors . . . . . . . 27
2.2.1 Mutators for Mutating Memristor to Meminductor . . . . 27
2.2.2 Mutators for Mutating Memristor to Memcapacitor . . . . 29
3 4-Port Metamutators and Their Realizations 33
3.1 Incognito Presence of Metamutators in Literature . . . . . . . . . 33
3.1.1 CCII+, CCII- Based Metamutator . . . . . . . . . . . . . 33
3.1.2 CCII+ and CF Based Metamutator . . . . . . . . . . . . . 39
3.1.3 CCII+ Based Metamutator . . . . . . . . . . . . . . . . . 43
3.1.4 Adder and Subtractor Metamutator . . . . . . . . . . . . . 47
3.2 New Designs for Metamutators with Two Active Devices . . . . . 50
3.2.1 Realization with One CFOA and One CCII+ . . . . . . . 51
3.2.2 Realization with Two DOCCII . . . . . . . . . . . . . . . 52
3.2.3 Realization with Two CFOA . . . . . . . . . . . . . . . . . 53
3.3 New Designs of Metamutators with Single Active Device . . . . . 54
3.3.1 Realization with Negative Type Fully Differential Current
Conveyor (FDCCII-) . . . . . . . . . . . . . . . . . . . . . 55
3.3.2 Realization with Dual X Current Conveyor (DXCCII) . . . 60
3.3.3 Realization with Newly Designed AD-IC . . . . . . . . . . 65
4 Different Applications of Metamutators 72
4.1 Realization of 1-ports . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.1.1 Mutating Nonlinear Resistor to Memristor . . . . . . . . . 73
4.1.2 Mutating Memristor to Meminductor . . . . . . . . . . . . 75
4.1.3 Mutating Memristor to Memcapacitor . . . . . . . . . . . 77
4.1.4 Floating and Grounded Impedance Scaling . . . . . . . . . 79
4.1.4.1 Inductance Simulator . . . . . . . . . . . . . . . . 81
4.1.4.2 Capacitance Multiplier . . . . . . . . . . . . . . . 82
4.1.4.3 Frequency Dependent Negative Resistor Simulator 84
4.1.5 RC-Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.2 Realization of 2-Ports . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.2.1 Transconductance Amplifier . . . . . . . . . . . . . . . . . 88
4.2.2 Transimpedance Amplifier . . . . . . . . . . . . . . . . . . 91
4.2.3 Voltage Mode Multiple Input Single Output Universal Filter 93
4.2.4 Current Mode Single Input Multiple Output Universal
Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5 Two Operationally Nonlinear Applications of AD-IC 103
5.1 Analog Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.2 Full-Wave Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6 Conclusion 113
List of Tables
1.1 Basic circuit elements. . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Constitutive relations of all memstors . . . . . . . . . . . . . . . . 5
1.3 Mutation table for realizing 1-port elements [4]. . . . . . . . . . . 16
2.1 Different circuit level realizations of M-R mutator. . . . . . . . . . 21
2.2 Two types and six circuit level realizations of M-L mutators. . . . 24
2.3 Two types and six circuit level realizations of M-C mutators. . . . 26
2.4 Two types and four circuit level realizations for ML-MR mutators. 28
2.5 Two types and four circuit level realizations for MC-MR mutators 29
3.1 Dimension of transistors used in CCII+ . . . . . . . . . . . . . . . 35
3.2 Dimension of transistors used in CCII- . . . . . . . . . . . . . . . 35
3.3 Dimension of transistors used in CF . . . . . . . . . . . . . . . . . 40
3.4 Dimension of transistors used in FDCCII- . . . . . . . . . . . . . 56
3.5 Dimension of transistors used in DXCCII . . . . . . . . . . . . . . 62
3.6 Dimension of transistors used in AD-IC . . . . . . . . . . . . . . . 65
3.7 Comparison between frequency range for optimal operation of
incognito metamutators in literature and newly designed of meta-
mutators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.8 General comparison between all types of mutators . . . . . . . . . 71
4.1 Equivalent impedance at the ports . . . . . . . . . . . . . . . . . 80
4.2 Different realizations of inductor . . . . . . . . . . . . . . . . . . . 81
4.3 Capacitance multiplier realizations . . . . . . . . . . . . . . . . . 83
4.4 FDNR realizations . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.5 Different 2-port applications and realizations with metamutators . 89
4.6 Different filter types depending on voltage source locations . . . . 95
4.7 Transfer functions of different filters . . . . . . . . . . . . . . . . . 96
4.8 Multifunctional filter realizations . . . . . . . . . . . . . . . . . . 99
4.9 Transfer function of different filters . . . . . . . . . . . . . . . . . 100
5.1 Transistor dimensions of the squarer circuits . . . . . . . . . . . . 105
5.2 Comparison of the proposed rectifier with others . . . . . . . . . . 112
viii
List of Figures
1.1 Basic circuit variables and fundamental 2-terminal elements . . . 2
1.2 The fourth element memristor completing the symmetry [1] . . . . 2
1.3 Symbol of memristor and its ϕ-q characteristic . . . . . . . . . . . 3
1.4 Block diagram of metamutator . . . . . . . . . . . . . . . . . . . . 14
1.5 (a) Block diagram, (b) Circuit level realization of VIM 4-port
metamutator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.6 (a) Block diagram, (b) Circuit level realization of CIM 4-port
metamutator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 (a) M-R mutator (b) M-L mutator (c) M-C mutator. . . . . . . . 20
2.2 The proposed memristor emulator circuit by L.Chua [1]. . . . . . 22
2.3 Implementation of M-R mutator with two CFOAs and one OpAmp 23
2.4 Circuit structure of grounded memristor emulator in [110] . . . . 23
2.5 Lossy memcapacitor emulator and lossy meminductor emulator . 30
2.6 MC-MR mutator circuit by Biolek et al. . . . . . . . . . . . . . . 31
2.7 MC-MR mutator circuit by Biolek et al. . . . . . . . . . . . . . . 31
2.8 CCII based meminductor, memcapacitor emulators [11] . . . . . . 32
2.9 Meminductor and memcapacitor emulation with dual-output CCII 32
3.1 The gyrator circuit by Sedra and Smith [22] . . . . . . . . . . . . 34
3.2 Diagram of the metamutator obtained from the gyrator circuit in
[22]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.3 Block diagram of CCII+ . . . . . . . . . . . . . . . . . . . . . . . 34
3.4 Block diagram of CCII- . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5 CMOS realization of: (a) (CCII+), (b) (CCII-) . . . . . . . . . . 36
3.6 Theoretical and simulation characteristics of i4 vs. i1 . . . . . . . 37
3.7 Theoretical and simulation characteristics of i3 vs. i2 . . . . . . . 37
3.8 Theoretical and simulation characteristics of v2 vs. v1 . . . . . . . 38
3.9 Theoretical and simulation characteristics of v3 vs. v4 . . . . . . . 38
3.10 Metamutator with CCII+ and CF [27] . . . . . . . . . . . . . . . 39
3.11 Block diagram of CF . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.12 CMOS realization of CF . . . . . . . . . . . . . . . . . . . . . . . 40
3.13 Theoretical and simulation characteristics of i1 vs. i3 . . . . . . . 41
3.14 Theoretical and simulation characteristics of i2 vs. i4 . . . . . . . 42
3.15 Theoretical and simulation characteristics of v4 vs. v1 . . . . . . . 42
3.16 Theoretical and simulation characteristics of v3 vs. v2 . . . . . . . 43
ix
3.17 CCII+ based inductor simulator proposed in [82] . . . . . . . . . 43
3.18 Diagram of metamutator extracted from [82] . . . . . . . . . . . . 44
3.19 Theoretical and simulation characteristics of i2 vs. i3 . . . . . . . 45
3.20 Theoretical and simulation characteristics of i1 vs. i4 . . . . . . . 45
3.21 Theoretical and simulation characteristics of v3 vs. v4 . . . . . . . 46
3.22 Theoretical and simulation characteristics of v2 vs. v1 . . . . . . . 46
3.23 Generalized 4-port mutator with adder and subtractor [24-26] . . 47
3.24 Block diagrams and defining relations of (a) adder, (b) subtractor. 48
3.25 Theoretical and simulation characteristics of i3 vs. i1 . . . . . . . 49
3.26 Theoretical and simulation characteristics of i4 vs. i2 . . . . . . . 49
3.27 Theoretical and simulation characteristics of v4 vs. v1 . . . . . . . 50
3.28 Theoretical and simulation characteristics of v3 vs. v2 . . . . . . . 50
3.29 Metamutator using CFOA and CCII+ . . . . . . . . . . . . . . . 51
3.30 Metamutator with two DOCCIIs . . . . . . . . . . . . . . . . . . 52
3.31 Metamutator realized with two CFOAs . . . . . . . . . . . . . . . 53
3.32 Block diagram of FDCCII- . . . . . . . . . . . . . . . . . . . . . . 55
3.33 CMOS realization of FDCCII- [84] . . . . . . . . . . . . . . . . . 56
3.34 CIM type metamutator realized with single FDCCII- . . . . . . . 57
3.35 VIM type metamutator realized with single FDCCII- . . . . . . . 58
3.36 Ideal and non-ideal gain of i1 and i2 . . . . . . . . . . . . . . . . . 58
3.37 Ideal and non-ideal gain of i2 and i3 . . . . . . . . . . . . . . . . . 59
3.38 Ideal and non-ideal gain of v2 and v3 . . . . . . . . . . . . . . . . 59
3.39 Ideal and non-ideal gain of v4 and v1 . . . . . . . . . . . . . . . . 60
3.40 Schematic block diagram of DXCCII . . . . . . . . . . . . . . . . 61
3.41 CMOS realization of DXCCII . . . . . . . . . . . . . . . . . . . . 61
3.42 Newly proposed metamutator with DXCCII . . . . . . . . . . . . 62
3.43 Ideal and non-ideal gain of i1 and i4 . . . . . . . . . . . . . . . . . 63
3.44 Ideal and non-ideal gain of i3 and i2 . . . . . . . . . . . . . . . . . 63
3.45 Ideal and non-ideal gain of v2 and v1 . . . . . . . . . . . . . . . . 64
3.46 Ideal and non-ideal gain of v4 and v3 . . . . . . . . . . . . . . . . 64
3.47 Schematic block diagram of AD-IC . . . . . . . . . . . . . . . . . 65
3.48 The implementation of AD-IC with twelve MOS transistors . . . . 66
3.49 Layout of the AD-IC circuit . . . . . . . . . . . . . . . . . . . . . 66
3.50 Schematic diagram of metamutator with AD-IC . . . . . . . . . . 67
3.51 Ideal and non-ideal gain of i3 and i4 . . . . . . . . . . . . . . . . . 68
3.52 Ideal and non-ideal gain of i1 and i2 . . . . . . . . . . . . . . . . . 68
3.53 Ideal and non-ideal gain of v3 and v2 . . . . . . . . . . . . . . . . 69
3.54 Ideal and non-ideal gain of v4 and v1 . . . . . . . . . . . . . . . . 69
4.1 Memristor realization with AD-IC based metamutator . . . . . . . 73
4.2 Implementation on non-linear load of M-R mutators. . . . . . . . 73
4.3 i− v characteristic of memristor . . . . . . . . . . . . . . . . . . . 75
4.4 Meminductor realization with memristor terminated metamutator 75
4.5 ϕ− i characteristic of meminductor . . . . . . . . . . . . . . . . 77
4.6 Memcapacitor realization with memristor terminated metamutator 78
4.7 q − v characteristic of the memcapacitor . . . . . . . . . . . . . . 79
4.8 Metamutator terminated with port impedances . . . . . . . . . . 79
4.9 Port n of metamutator terminated with impedance Zn . . . . . . 80
4.10 Impedance scaling calculated with signal flow-graph . . . . . . . . 80
4.11 Phase and |impedance| plots of the inductor vs. frequency . . . . 82
4.12 Phase and |impedance| plots of the capacitor vs. frequency . . . . 83
4.13 Schematic of fully digital receiver [31] . . . . . . . . . . . . . . . . 84
4.14 Characteristics of FDNR in frequency domain . . . . . . . . . . . 85
4.15 Block diagram of the RC-oscillator . . . . . . . . . . . . . . . . . 86
4.16 Simulation result of RC-oscillator . . . . . . . . . . . . . . . . . . 88
4.17 Transconductance amplifier realization #4 . . . . . . . . . . . . . 90
4.18 I/O characteristics vs. frequency of transconductance amplifier . . 91
4.19 Circuit of transimpedance amplifier realization #2 of Transimpedance
Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.20 I/O characteristics vs frequency of transimpedance amplifier . . . 92
4.21 Universal filter structure . . . . . . . . . . . . . . . . . . . . . . . 94
4.22 VIM based VM-MISO universal filter . . . . . . . . . . . . . . . . 95
4.23 Simulation results of all filter types . . . . . . . . . . . . . . . . . 96
4.24 Circuit diagram of the CM-SIMO universal filter . . . . . . . . . . 99
4.25 Current mode filter realization #4 . . . . . . . . . . . . . . . . . 100
4.26 Simulation results of all type filters . . . . . . . . . . . . . . . . . 101
5.1 Block diagram of proposed multiplier . . . . . . . . . . . . . . . . 104
5.2 Voltage in/current out squarer circuits: (a) NMOS-based, (b)
PMOS-based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.3 Simulation result of multiplier as modulator . . . . . . . . . . . . 107
5.4 Block diagram of AD-IC . . . . . . . . . . . . . . . . . . . . . . . 109
5.5 Time-domain input and output waveforms of the rectifier with
AD-IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.6 DC characteristics of the non-inverting full-wave rectifier circuit . 111
5.7 PDC ,P(RMS) characteristics of the rectifier in 100mV input ampli-
tude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
List of Abbreviations
AC Alternative Current
ADC Analog to Digital Converter
AD-IC Additive- and Differentiative Integrated Circuit
AM Amplitude Modulator
Ap All Pass
BP Band Pass
CCCDBA Current Controlled Current Differencing BufferedAmplifiers
CCCII Current Controlled Current Conveyor
CCII+ Plus Type II. generation Current Conveyor
CCII- Minus Type II. generation Current Conveyor
CF CurrentFollower
CFOA Current F eedback O perational Amplifier
CIM CurrentInverting Metamutator
CM CurrentMode
CMOS Complementary Metal Oxide Semiconductor
DC Direct Current
DOCCII Dual Output Current Conveyor
DO-OTA Dual Output Operational Transconductance Amplifier
DSBSC Double Sideband Suppressed Carrier Alternative Current
DVCC Differential Voltage Current Conveyor
DXCCII DualX Current Conveyor
FDCCII Fully Differential Current Conveyor
FDNR Frequency Dependent Negative Resistor
HP Hewllet Packard
xii
HP High Pass
JFET Junction Field Effect Transistor
KCL Kirchoff’s Current Law
KVL Kirchoff’s Voltage Law
LP Low Pass
MC MemCapacitor
ML MemInductor
MR MemRistor
NMOS Negative Metal Oxide Semiconductor
OPAMP OPerational AMPlifier
OTA Operational Transconductance Amplifier
PMOS Positive Metal Oxide Semiconductor
TSMC Taiwan Semiconductor Manufacturing Corporation
VIM Voltage Inverting Metamutator
VM Voltage Mode
xiii
Chapter 1
Introduction
1.1 Basic Circuit Elements and Memstors
As it is well known there are four basic circuit variables: electrical charge q, cur-
rent i (being the derivative of charge), voltage v and flux ϕ (being the derivative of
flux); also only three fundamental, two-terminal circuit elements were known and
used: resistor, capacitor and inductor. The behavior of these circuit elements
is described by an algebraic relationship between two of the four basic circuit
variables.
fR(i, v) = 0 Resistor
fC(q, v) = 0 Capacitor
fL(ϕ, i) = 0 Inductor
Table 1.1: Basic circuit elements.
According to Table 1.1 a symbolic graph can be visualized that depicts the con-
stitutive (defining) relations between current-voltage, charge-voltage and flux-
current respectively as shown in Figure 1.1. It is the missing link between flux ϕ
and electrical charge q that led to the discovery of memristor.
In 1971, Leon Chua completed the symmetry by introducing the relation between
ϕ and q and, calling the resulting element a memristor an acronym obtained by
combining MEMory and ResISTOR. Thus a memristor is a 2-terminal circuit
element with an algebraic constitutive relation between its charge and flux [1].
1
Figure 1.1: Basic circuit variables and fundamental 2-terminal elements
Figure 1.2: The fourth element memristor completing the symmetry [1]
The general expression of a time-invariant memristor is:
fM(ϕ, q) = 0 (1.1)
The symbol and a hypothetical ϕ-q curve of the memristor are shown in Figure
1.3.
2
Figure 1.3: Symbol of memristor and its ϕ-q characteristic
Based on dependency between charge and flux of memristor there are two types
of memristors: charge controlled and flux controlled memristors.
If ϕ is a function of q the memristor is charge controlled, if q is a function of ϕ
the memristor is flux controlled. For a charge controlled memristor:
ϕ = f(q) (1.2)
Assuming that f in (1.2) is differentiable, by taking time derivative of both sides
of (1.2) and applying the chain rule the v-i dependence for a memristor becomes:
dϕ(t) df(q) dq
v(t) = = . = M(q(t)).i(t) (1.3)
dt dq dt
Thus,
v(t) = M(q(t)).i(t) (1.4)
where M(q(t)) = df(q)/dq is the Memristance with Ohm (Ω) as unit, justifying
the inclusion of “ristor” into the name.
In a flux controlled memristor the charge q is a function of ϕ,
q = f(ϕ) (1.5)
3
Again by taking time derivative of both sides of (1.5) and applying the chain rule,
(1.6) becomes:
dq(t) df(ϕ) dϕ
i(t) = = . = W (ϕ(t)).v(t) (1.6)
dt dϕ dt
Thus,
i(t) = W (ϕ(t)).v(t) (1.7)
where W (q(t)) = df(ϕ)/dϕ is Memductance and has the unit of Siemens (f).
Comparing (1.4) and (1.7), one obtains:
1
M(q(t)) = (1.8)
W (ϕ(t))
Again from (1.4) and (1.7) it is easily observed that when the current through
the memristor is zero its voltage is also zero, and vice versa thus forcing the
characteristic to go through the origin. Thus by applying a sinusoidal current
or voltage signal to the memristor its current-voltage characteristic becomes a
Lissajous curve also passing through the origin.
In 1976, Chua and Kang in [2] introduced memristive systems by extending the
concept of memristor to a class of nonlinear dynamical systems and in 2010 Ventra
et al. extended the notion of memristive systems to capacitive and inductive ele-
ments with properties depending on the state and history of the system just like
memristor [3]. By applying sinusoidal inputs all these elements show pinched hys-
teretic loops between two constitutive variables that define them: current-voltage
for memristor, charge-voltage for memcapacitor, and current-flux for meminduc-
tor.
4
Finally, it should be observed that for a linear memristor M(q) and W (ϕ) re-
duce to constants hence to simple linear resistors, explaining why memristor was
discovered so late.
Memstor, a term introduced in [4], is a generic name for the class of 2-terminal
elements with memory such as memristor, meminductor, memcapacitor, which
are devices whose terminal behavior depends nonlinearly on the initial state and
the history of the applied input to the system. All memstors are summarized in
Table 1.2 where σ is the time integral of charge and ρ is the time integral of flux.
Charge-controlled memristor ( ∫ t )
v(t) = M q0 + i(τ)dτ i(t)
0
Flux-controlled memristor ( ∫ t )
i(t) = W ϕ0 + v(τ)dτ v(t)
0
Charge-controlled memcapacitor ( ∫ t )
v(t) = DM σ0 + q(τ)dτ q(t)
0
Flux-controlled memcapacitor ( ∫ t )
q(t) = CM ϕ0 + v(τ)dτ v(t)
0
Charge-controlled meminductor ( ∫ t )
ϕ(t) = LM q0 + i(τ)dτ i(t)
0
Flux-controlled meminductor ( ∫ t )
i(t) = ΓM ρ0 + ϕ(τ)dτ ϕ(t)
0
Table 1.2: Constitutive relations of all memstors
5
1.2 Literature Review
In 1968 Leon Chua in [5] claimed that it is possible to mutate one type of circuit
element, be it linear or nonlinear, into another by using a 2-port mutator and
he first proposed three types of mutators for this purpose. Then in 1971, after
introducing “memristor” as the fourth circuit element, he presented the first M-
R mutator circuit with a highly complex structure for the purpose of realizing
memristors from nonlinear resistors [1].
Due to the invaluable properties of memristor such as non-volatile memory ele-
ment and/or its nonlinear characteristics, this element has been used in various
applications like the design of analog and digital circuits, neuromorphic circuits,
chaotic systems etc. [6], [84], [85], [86], [87].
Hewlett Packard (HP) research team in 2008 successfully realized the first mem-
ristor as a simple 2-terminal device using thin film Titanium dioxide (TiO2),
which can be viewed as a 2-terminal resistor with changing resistance depending
on the voltage or current applied to it [83]. Despite this successful realization,
memristors are not yet commercially available and their modeling is essential to
memristor based circuit and system design. Thus researchers have been encour-
aged to develop simple SPICE macro models [120-124].
Another approach is the use of mutator circuits, constructed using off-the-shelf
devices which are commercially available in the market [98-102], [104-105], [107],
[109-112] to mutate the dynamic behavior of conventional elements to that of
a memristor hence the need and emphasis on “Mutators”. Mutators not only
convert one type of element to another in simulations they also make hard real-
izations of unavailable 2-terminal elements possible and thus provide means to
experiment in the lab with them.
A literature survey shows a very large number of mutator realizations, possessing
weaknesses such as:
6
i. The use of an excessive number of active elements,
ii. Excessive use of grounded and/or floating passive elements,
iii. Usage of ungrounded capacitors; using grounded capacitors in integrated cir-
cuit (IC) implementation has considerable advantages [116],
iv. Use of analog multiplier for the purpose of obtaining nonlinearity property of
memristor, causes to increasing the number of used active elements , which
resulting in higher power consumption also large chip area occupation.
For instance, the memristor emulator presented in [113] uses a Microcontroller,
an Analog to Digital Converter (ADC) and a Digital to Analog Converter (DAC)
blocks and one low pass filter. This emulator is topologically complex which
limits its applicability due to difficulty in interconnecting with active and passive
devices. The proposed emulator circuit suffers from weakness i.
An Electronically Tunable Differential Different Current Conveyor (EDDCC) and
a multiplier are used to implement the memristor emulator circuit proposed in
[114]. Six OTAs are employed in the structure of EDDCC. However, the ex-
perimental results using this mutator circuit do not satisfy the properties of a
memristor and the hysteresis loop area does not decrease as frequency increases.
Also, the proposed emulator circuit suffers from weaknesses i and iv.
A CMOS based memristor emulator has been introduced in [115]. Single CCII+,
one grounded capacitor and one Voltage Controlled Resistor (VCR) are employed
in the implementation of the emulator. Also, two OPAMPs, a single transistor,
two floating capacitors and six resistors are utilized in VCR implementation.
Due to complexity of the structure and use of floating capacitors this emulator
configuration is not suitable for real world hardware applications. Briefly the
proposed emulator circuit suffers from disadvantages i, ii and iii.
In [98] a floating memristor with four OPAMPs, single analog multiplier, ten
transistors, single capacitor and eight resistors in its structure was presented.
7
Both simulation and experimental results are given in the paper. There are
three important properties to be considered in a memristor emulator: memory
effect, frequency dependent characteristic, and nonlinearity. Memory effect and
frequency dependency characteristic are obtained by using a capacitor. Nonlin-
earity is implemented using multiplier circuit. But each used block gives rise to
extra power dissipation and more complex circuit also, simulations have not been
performed at transistor level. Briefly proposed mutator circuit suffers from i, iii
and iv.
Yesil et al. proposed a floating memristor emulator employing a single Differential
Difference Current Conveyor (DDCC), one analog multiplier and two resistors,
one floating and one grounded capacitor [99]. The capacitor provides the memory
effect and the multiplication of capacitor and resistor voltages is connected to the
Y terminal of the active device. However, the memristor can be operated only
at high frequencies such as in the order of MHz which contradicts the essential
properties of memristor also, the proposed mutator circuit suffers from weakness
i.
In [100] a floating memristor emulator including four CFOAs, one multiplier and
six passive elements in its structure have been proposed. Both simulation and
experimental results are given in the paper. However, the simulations are not
done at transistor level and the proposed memristor mutator circuit suffers from
i, ii, iv.
In [101] a floating memristor emulator containing four CFOAs, single analog
multiplier, single OPAMP and nine passive elements, where some of the elements
are floating is presented. The memristance value of obtained memristor is not
electronically tunable. The emulator circuit is complex, bulky, suffering from i,
ii, iv.
In [104], a grounded memristor emulator made of two CFOAs, a single analog
multiplier and seven grounded/floating passive elements has been proposed. The
8
optimal frequency range of the obtained memristor is 16Hz - 160kHz. Both sim-
ulation and experimental results of the presented memristor emulator have been
given to confirm its feasibility and workableness. However, the simulations are
not at transistor level and commercially available active devices have been used
instead of CFOAs and analog multiplier. The proposed memristor mutator circuit
suffers from weakness i, ii and iv.
A CCII based charge controlled memristor emulator containing single CCII, single
analog multiplier, single floating resistor and a grounded capacitor was presented
in [105]. However, the memristance value of obtained memristor is not electroni-
cally tunable. Also, commercially available active devices AD633 and AD844 have
been utilized instead of multiplier and CCII+, respectively. Briefly the proposed
emulator circuit suffers from disadvantages i, ii and iv.
A tunable floating memristor emulator circuit consisting of single multiple-output
OTA (MO-OTA), single analog multiplier and two grounded passive elements was
proposed in [106]. This emulator derived from the one in [99] has the advantage
of its memristance value being adjustable by biasing the current of the OTA. The
proposed emulator, despite its simplicity in design, suffers from iv.
One grounded voltage controlled and one grounded current controlled memristor
emulators were reported in [107]. In the structure of current-controlled memristor
emulator, two CCII+s, a single analog multiplier, a single buffer as active devices
and three grounded one floating passive components are being used, while the
voltage controlled memristor emulator consists of three CCII+s, a single analog
multiplier, single buffer and six grounded passive elements. The circuit structures
of both mutators are highly complex and suffer from weakness i, ii and iv. Also,
the memristance values of obtained memristors are not electronically tunable.
Using single Current Backward Transconductance Amplifier (CBTA), single ana-
log multiplier, two resistors and one grounded capacitor, a grounded memristor
emulator is proposed in [108]. In this emulator Memory effect and frequency
dependency properties of memristor are implemented by using a capacitor and
9
the nonlinearity property is obtained by using multiplier. The proposed emulator
suffers from iv.
In [3] Pershin and Ventra, using off-the-shelf components like one microcontroller,
one Analog to Digital Converter (ADC) and one digital potentiometer with its
resistance defined by a digital code written in it, built a rather complex and
expensive floating memristor emulator. The proposed memristor emulator suffers
from i and ii.
In [102], a new floating memristor emulator consisting of three OTAs, four CCIIs,
and seven passive elements, three of them floating, has been presented. Both sim-
ulation and experimental results of the presented memristor emulator have been
given to confirm its feasibility and workability. Commercially available active de-
vices CA3080 and AD844 have been used instead of OTA and CCII in simulations
and experiments. However, the circuit configuration is complex and bulky and
suffers from weaknesses i and ii.
In [103] a floating memristor emulator has been presented. The circuit of the em-
ulator consists of one OTA, one multiplier, two MOS transistor and two grounded
capacitors. The memristance value cannot be tuned electronically. The proposed
emulator circuit suffers from iv.
A grounded memristor emulator employing ten DDCC active elements, eight
transistors and five passive elements has been presented in [109]. However, the
proposed emulator circuit suffers from i and ii. Each active device giving rise to
extra power dissipation and a more complex circuit.
A generalized mutator for the purpose of realizing inductors, memristors, me-
minductors and memcapacitor has been reported in [4]. The memristor can be
obtained by employing single adder, single subtractor, grounded diode, floating
inductor and capacitor, without using an analog multiplier. The diode provides
the non-linear resistor in the circuit. This circuit is able to convert all types of
10
circuit elements to each other and the idea of metamutator was first introduced
in this article.
Two grounded memristor emulator configurations were presented in [110]. Each
circuit comprises three CFOAs, four resistors, two capacitors, and one diode
without using an analog multiplier. Nonlinear characteristic is provided by a
diode. CFOA which is an active element, is modeled by AD844, a commercially
available active device, and experimental results have been provided. Likewise,
in [111], comprising of two CFOAs, a single OTA and five grounded passive
elements a grounded memristor emulator again without using an analog multiplier
is introduced. The proposed emulator circuits suffer from i and ii.
In [112] a grounded memristor emulator including Single Differential Voltage Cur-
rent Conveyor Transconductance Amplifier (DVCCTA), one grounded capacitor,
three resistors, one of them floating, is presented. Both simulation and experimen-
tal results of the memristor emulator are given in the paper. As for experiments
a single CA3080, four AD844s and nine passive elements provided the imple-
mentation of DVCCTA. Due to its highly complex structure this emulator is not
suitable for IC designs. The proposed emulator circuit suffers from i and ii.
In [119] a memristor emulator based on a light dependent resistor (LDR), with
its resistance easily reconfigurable by a controlling voltage, is introduced. How-
ever, the memristance value of the memristor, realized due to the nonlinearity of
the LDR, is hard to calculate accurately. Also the complexity and difficulty of
practical implementation of the introduced emulator are the other disadvantages.
The proposed emulator circuit suffers from i. ii and iii.
Memcapacitive and meminductive systems are two classes of circuit elements with
memory that complete memstors ie. the class of memristive systems [1,2]. When
driven by a periodic input, their characteristics are hysteretic loops between their
constitutive variables current–flux for meminductors and voltage–charge for mem-
capacitors which pass through the origin [118]. Meminductor and memcapacitor
are able to store energy and this significant ability distinguishes these elements
11
from memristor. Due to lack of availability of meminductor and memcapacitor
as off the shelf components, just like the memristor, there are many different em-
ulator circuits in literature for simulating meminductor and memcapacitor with
active and passive components together.
In 2010 Pershin and Ventra, by using one OpAmp and several passive compo-
nents, introduced mutator circuits for realizing lossy meminductors and lossy
memcapacitors from memristors [7]. In simulations they have used the memristor
emulator circuit in [3] and shown an interesting connection between three memory
elements. The proposed emulator circuit suffers from iii.
In [8] a mutator circuit for mutating memristor to memcapacitor by employing
inexpensive off-the-shelf components like, two OTAs and several passive com-
ponents was reported. The presented mutator provides a true memristor into
memcapacitor mutation. However, the proposed mutator is able to mutate only
memcapacitor from memristor Also, simulations are not in transistor levels and
for OTAs AD844 commercial device is used. In [9] mutator circuit for mutating
memristor to memcapacitor is presented. The main idea of circuit design is the
same as [8] and instead of two OTAs one CCII+ and one OTA is used in the struc-
ture of mutator circuit. In simulations the constitutive relation of the memristor
is preserved, within scaling, by the elements obtained after the mutation Also
simulation results confirm an important fingerprint of mem-elements, namely the
gradually decreasing hysteretic effects with increasing input frequency. However,
gain simulations have not been done at transistor level and AD844 commercial
device is used instead.
In [11] different current conveyor based mutator implementations for converting
memristor to both meminductor and memcapacitor have been proposed. Some of
the implementations use a floating memristor. However only theoretical analyses
are presented. Also, it is difficult to carry out these meminductor and memcapaci-
tor mutators in practice since a reliable floating memristor emulator is necessarily
required. Also the proposed circuits suffer from ii.
12
In 2014 Liang et al. presented a practical floating memristorless meminductor
emulator circuit, using simple and inexpensive off-the-shelf components like four
CCII+s, two operational OPAMPs, single analog multiplier, and several passive
components in [16]. The proposed mutator circuit suffers from all of drawbacks
mentioned above (i,ii,iii and iv). Also in simulations commercially available active
devices CA3080 and AD844 have been utilized instead of CMOS based OTA and
CCII, respectively and simulations have not been done at transistor levels.
It is very important to observe that all of the above mutator simulators/emulators
can only serve one purpose namely, that of behaving like a 2-port mutator for
mutating one circuit element to a memstor. The 4-port metamutator used in this
thesis, besides behaving like a mutator, is a multi-purpose device that can be
used in realizing/simulating/emulating many electronic devices such as Universal
Filters, Transconductance/Transimpedance Amplifiers, Oscillators, Rectifiers and
many more.
1.3 Generalized 4-Port Mutators: Metamutators
The first hard-realization shown in Figure 1.4 of memristor using a highly complex
mutator circuit was introduced in [1]. Since then different types of much simpler
mutator circuits have been proposed for realizing memristors using nonlinear
resistors or memstors from memristor which were briefly described in Section
1.2.
The idea of a multi-functional 4-port mutator was first introduced in [4], then
under the name of “Generalized Mutative 4-port” in [25] and then named as
“Metamutator” because of its ability to implement a variety of elements/systems
like memstors*, mutators, trans-admittance/trans-impedance amplifiers, multi-
functional universal filters, quadrature oscillators, inverters, gyrators, multipliers
etc. when some of its ports are properly terminated. Several IC designs of
metamutators have been proposed and discussed in [12-14] and [24-26].
13
The general schematic block diagram of a metamutator is shown in Figure 1.4.
Figure 1.4: Block diagram of metamutator
According to the minus sign in the voltage or current in one of the ports, the
class of metamutators can be separated into two sub-classes:
1. Voltage Inverting Metamutators (VIM)
2. Current Inverting Metamutators (CIM)
The 4-port block diagrams of VIM and CIM are shown in Figure 1.5 and Figure
1.6 and their mathematical port descriptions are defined via the equalities (1.9)
and (1.10) respectively. Although identity matrices show in both expressions in
VIM a port voltage is being inverted whereas, in CIM a port current is being
inverted.
     
ik  1 0 0 0  im 

    
il
 
 
 = 
0 1 0 0
vm 0 0 1 0× 
 in  vl  (1.9)
vn 0 0 0 1 −vk
14
Figure 1.5: (a) Block diagram, (b) Circuit level realization of VIM 4-port meta-
mutator
Figure 1.6: (a) Block diagram, (b) Circuit level realization of CIM 4-port meta-
mutator
     
ik
 il 
 1 0 0 0  im 
  = 

vm 
0 1 0 0  −i × 0 0 1 0 
n
  (1.10)vl
vn 0 0 0 1 vk
In (1.9) and (1.10) attention should be paid to port voltages’ and port currents’
reference directions; due to the – sign for the voltage vk in (1.9) and the – sign
for the current in in (1.10). Care must be exercised in the implementation phase
as to which variable follows the other in (1.9) and (1.10); variables have been
indexed with letters k, l,m, n taking different values from the set {1,2,3,4}.
15
These metamutators all share the same port descriptions hence possess the com-
mon property of becoming a different X-Y type mutator depending on how two of
the ports are terminated. This in turn makes possible, via so created mutators,
of mutating classical circuit elements to memstors or memstors to memstors. All
of these terminations and mutations are listed in Table 1.3.
# Port k Port m Port l Port n Out Element
put
Port
1 Resistor Capacitor Memristor - n Meminductor
2 Capacitor Resistor - Memristor l Meminductor
3 Memristor - Resistor Capacitor m Meminductor
4 - Memristor Capacitor Resistor k Meminductor
5 Memristor Inductor Resistor - n Memcapacitor
6 Inductor Memristor - Resistor l Memcapacitor
7 Resistor - Memristor Inductor m Memcapacitor
8 - Resistor Inductor Memeristor k Memcapacitor
9 Capacitor - Inductor NL Resistor m Memristor
10 NL Resistor Inductor - Capacitor l Memristor
11 - Capacitor NL Resistor Inductor k Memristor
12 Inductor NL Resistor Capacitor - n Memristor
Table 1.3: Mutation table for realizing 1-port elements [4].
1.4 Thesis Outline
In the first chapter of this thesis a brief introduction to basic circuit elements
together with a new class of memory elements namely, memstors have been pre-
sented. In the same chapter, the necessity of using mutators and previously
developed mutator circuits in the literature have been studied. Also a brief in-
troduction to 4-port metamutators, their classification, according to their port
description matrices, into two categories, Voltage Inverting Metamutator (VIM)
and Current Inverting Metamutator (CIM) have been presented.
In the second chapter the necessity of using mutators and the basic definition of
2-port mutators with their ports relation matrices and the mutators themselves
16
for mutating nonlinear circuit elements to memristors or converting memristors
to other non-volatile circuit elements like meminductor and memcapacitor have
been presented also some of the previously developed classical mutator circuits,
well-known in the literature, have been investigated.
In the literature there are many incognito 4-port mutator structures embedded
in electronic circuits such as simulators/emulators. Nobody has been able to
identify these underlying 4-ports and their ability to act as a Metamutator. With
the third chapter in addition to introducing some of these incognito metamutator
realizations, newly designed metamutator circuits, with one or two active devices
in their structures, have been presented. Also, a novel realization of metamutator
with a new single active device, Additive and Differential IC (AD-IC) along with
the implementation of AD-IC with twelve transistors, has been proposed.
In the fourth chapter, different applications of metamutators developed during
the research period of this thesis have been presented. As the port description
matrix of all introduced metamutators in Chapter 3 are the same, all of these
applications stand true for all of metamutators. Depending on how some of the
ports are terminated, metamutator applications, can be classified in two groups,
as follows:
I. 1-port circuits realized with metamutators,
II. 2-port circuits realized with metamutators.
For example, in 1-port realizations, by properly terminating three ports of the
metamutator the resulting circuit may behave as mutator, floating and/or grounded
impedance scalor, RC- oscillator. On the other hand, in 2-port realizations, by
properly terminating two ports of the metamutator the resulting circuit may
behave like a transconductance amplifier, transimpedance amplifier, voltage or
current mode multiple input single output universal filter and single input mul-
tiple output universal filter. All of these applications have been presented in
17
Section 4.2 and examined in detail with PSPICE simulations using transistor pa-
rameters obtained from layout level descriptions of metamutators; comparison of
simulation and theoretical results have also been presented in the same section.
In the fifth chapter of this thesis a voltage multiplier with single AD-IC and two
squarer circuits in its structure and a full-wave rectifier again with an AD-IC
and two diodes in its configuration have been presented. Both of the circuits
were simulated with parameters extracted from the layout and simulation results
show very good conformity with desired voltage multiplier and full-wave rectifier
behaviors. Also a comparison of the proposed analog multiplier and full-wave
rectifier with others, existing in the literature, are included into this chapter.
Conclusions and future research directions conclude the thesis in the fifth chapter
followed by a list of references and appendices containing PSPICE Netlists and
other implementation programs.
18
Chapter 2
Mutator Circuits and Memstor Simulations
First in 1968 Leon Chua in [5] claimed that it is possible to mutate one type of
circuit element, be it linear or nonlinear, into another by using a two-port mutator
and he first proposed three types of mutators for mutating circuit elements to each
other. In 1971, he also presented a new class of mutators, for mutating nonlinear
circuit elements to memristors and vice versa [1]. According to [1] there are
several types of circuit realizing the same kind of mutators which mutate element
type X into element type Y, called X-Y mutator. The symbolic 2-port structures
of these mutators are shown in Figure 2.1.
19
Figure 2.1: (a) M-R mutator (b) M-L mutator (c) M-C mutator.
The M-R, M-L, and M-C mutators which will be presented in this chapter, mu-
tate a resistor or capacitor or inductor, all non-linear into a memristor. The
basic principle of these types of mutations is preserving the “shape” of the non-
linear characteristic of the R, C and L type elements, which are mutated into the
corresponding charge-flux constitutive relation of the memristor.
2.1 Mutators for Mutating Nonlinear Circuit Elements to Memristor
2.1.1 Mutators for Mutating Nonlinear Resistor to Memristor
Two types and four circuit level realization for mutating nonlinear resistors to
memristors are proposed by Chua as shown in Table 2.1.
20
Table 2.1: Different circuit level realizations of M-R mutator.
Both type of mutators convert voltage-current characteristic of the nonlinear re-
sistor at port 2 to that of a memristor with same characteristic at port 1 but
with a minor difference: for Type-1 vR-iR characteristic is mutated to a ϕM -qM
characteristic whereas for Type-2 to that of a qM -ϕM characteristic.
General definitions of time-invariant nonlinear resistor and memristor are given
in (2.1) and (2.2),
fR(vR, iR) = 0 (2.1)
where vR, iR are the voltage and the current of the nonlinear resistor,
fMR(ϕM , qM) = 0 (2.2)
where qM , ϕM are the electric charge and flux of the memristor respectively.
21
In type one, the similarity of characteristics (2.1) and (2.2) can be observed by a
linear transformation (a scaling to be more precise) of the coordinates as in (2.3).
 qM = Ky.iR (2.3)ϕM = Kx.vR
In type two, the similarity of characteristics (2.1) and (2.2) can be observed by
linear transformations of the coordinates as in (2.4).
 qM = Kx.vR (2.4)ϕM = Ky.iR
where Kx and Ky are real constants with values depending on how the mutator
is designed.
The first nonlinear resistor to memristor mutator circuit is shown in Figure 2.2.
The M-R mutator of type 1, circuit level realization 1, was selected in [1]. In the
circuit implementation of this mutator two operational amplifiers, 14 transistors,
and a number of passive components were employed.
Figure 2.2: The proposed memristor emulator circuit by L.Chua [1].
22
In 2011 Biolek and Biolkova, by using off-the-shelf components like one Oper-
ational Amplifier (OpAmp) and two Current Feedback Operational Amplifiers
(CFOA), and several passive elements introduced a mutator circuit shown in
Figure 2.3 for mutating nonlinear resistors into memristors [10].
Figure 2.3: Implementation of M-R mutator with two CFOAs and one OpAmp
In 2014 a grounded memristor emulator circuit including three CFOAs, two resis-
tors, two capacitors and one nonlinear resistor was presented in [110]. The circuit
structure is shown in Figure 2.4.
Figure 2.4: Circuit structure of grounded memristor emulator in [110]
2.1.2 Mutators for Mutating Nonlinear-Inductor to Memristor
Two types and six circuit level realizations for mutating nonlinear inductor to
memristor are proposed by Chua in [1], as shown in Table 2.2.
Both type of mutators convert ϕL-iL characteristic of the time-invariant nonlinear-
inductor at port two to that of a memristor with same characteristic at port one
23
Table 2.2: Two types and six circuit level realizations of M-L mutators.
but with a minor difference: for Type-1 ϕL-iL characteristic is mutated to a
ϕM -qM whereas for Type-2 to that of a qM -ϕM characteristic.
In the sequel some generalized 4-ports will be so designed that both types of
mutators can be obtained with proper termination of two of the ports.
General definitions of time-invariant nonlinear-inductor and memristor are given
with:
fL(iL, ϕL) = 0 (2.5)
where iL, ϕL are current and flux of the nonlinear-inductor respectively.
fMR(qM , ϕM) = 0 (2.6)
24
where qM -ϕM are charge and flux of the memristor respectively.
In type one, the similarity of characteristics (2.5) and (2.6) can be observed by
linear transformations of the coordinates as in (2.7).
 ϕL = Kx.ϕM (2.7)iL = Ky.qM
In type two, the similarity of characteristics (2.5) and (2.6) can be observed by
linear transformations of the coordinates as in (2.8).

 ϕL = Kx.qM (2.8)iL = Ky.ϕM
where Kx and Ky are real constants with values depending on how the mutator
is designed.
2.1.3 Mutators for Mutating Nonlinear-Capacitor to Memristor
Two types and six circuit level realizations for mutating a time-invariant nonlinear-
capacitor to a memristor proposed by Chua in [1] are shown in Table 2.3.
Both type of mutators convert the qC-vC characteristic of the time-invariant
nonlinear-capacitor at port two to that of a memristor with the same charac-
teristic at port one but with a minor difference: for Type-1 qC-vC characteristic
is mutated to a qM -ϕM whereas for Type-2 to that of a ϕM -qM characteristic.
In the sequel a generalized mutative 4-port will be so designed that all types of
mutators can be obtained with proper termination of two of the ports.
General definitions of nonlinear-capacitor and memristor are given with (2.9) and
(2.10) respectively.
25
Table 2.3: Two types and six circuit level realizations of M-C mutators.
fC(qC , vC) = 0 (2.9)
where qC , vC are the charge and voltage of the nonlinear-capacitor respectively.
fMR(qM , ϕM) = 0 (2.10)
where qM , ϕM are the charge and the flux of the memristor.
In type one, the similarity of characteristics (2.9) and (2.10) can be observed by
linear transformations of the coordinates as in (2.11).

 qM = Kx.qC (2.11)ϕM = Ky.vC
26
In type two, the similarity of characteristics (2.9) and (2.10) can be observed by
linear transformations of the coordinates as in (2.12)
 qM = Kx.vC (2.12)ϕM = Ky.qC
where Kx and Ky are real constants with values depending on how the mutator
is designed.
2.2 Mutators for Mutating Memristor to Other Memstors
Biolek et al. in 2010, inspired by Chua’s mutator circuits, proposed two classes
of mutators for mutating memristor to meminductor and memristor to memca-
pacitor [9]. Each of these classes has two types and four circuit level realizations.
2.2.1 Mutators for Mutating Memristor to Meminductor
The circuit level realizations of ML-MR mutator which are extracted from [9],
are illustrated in Table 2.4.
Both type of mutators convert qM , ϕM characteristic of the memristor at port
two to that of a meminductor with the same characteristic at port one but with
a minor difference: for Type-1 qM , ϕM characteristic is mutated to a ρL-qL char-
acteristic whereas for Type-2 to that of a qL-ρL characteristic.
General definitions of memristor and meminductor are given as:
fMR(qM , ϕM) = 0 (2.13)
where ϕM -qM are the charge and flux of the memristor respectively.
27
Table 2.4: Two types and four circuit level realizations for ML-MR muta-
tors.
fML(qL, ρL) = 0 (2.14)
where qL and ρL are the charge and the time integral of flux of the meminductor.
In type one, the similarity of characteristics (2.13) and (2.14) can be observed by
linear transformations of the coordinates as in (2.15).
 qL = Ky.ϕM (2.15)ρL = Kx.qM
In type two, the similarity of characteristics (2.13) and (2.14) can be observed by
linear transformations of the coordinates as in (2.16).
 qL = Ky.qM (2.16)ρL = Kx.ϕM
where Kx and Ky are real constants with values depending on how the mutators
are designed.
28
2.2.2 Mutators for Mutating Memristor to Memcapacitor
The circuit level realizations of MC-MR mutator, which are extracted from [9],
are illustrated in Table 2.5.
Table 2.5: Two types and four circuit level realizations for MC-MR muta-
tors
Both type of mutators convert qM , ϕM characteristic of the memristor at port
two to that of a memcapacitor with same characteristic at port one but with a
minor difference: for Type-1 ϕM -qM characteristic is mutated to a ϕC-σC whereas
for Type-2 to that of a σC-ϕC characteristic.
General definitions of memristor and memcapacitor are given as
fMR(ϕM , qM) = 0 (2.17)
where qMR and ϕMR are charge and flux of memristor respectively.
fMC(σC , ϕC) = 0 (2.18)
where σC and ϕC are time integral of charge and flux of memcapacitor.
29
In type one, the similarity of characteristics (2.17) and (2.18) can be observed by
linear transformations of coordinates as in (2.19)

 σC = Kx.qM (2.19)ϕC = Ky.ϕM
In type two, the similarity of characteristics (2.17) and (2.18) can be observed by
linear transformations of coordinates as in (2.20),

 σC = Kx.ϕM (2.20)ϕC = Ky.qM
Where Kx and Ky are real constants with values depending on how the mutators
are designed.
Again in 2010 Pershin and Ventra, by using one OpAmp and several passive
components, as shown in Figure 2.5, introduced mutator circuits for realizing
lossy meminductors and lossy memcapacitors from memristors [7]. In simulations
they have used the memristor emulator circuit in [3] and shown an interesting
connection between three memory elements.
Figure 2.5: Lossy memcapacitor emulator and lossy meminductor emulator
In 2010, Biolek et al., proposed a circuit for converting memristors to memca-
pacitors by employing two Operational Transconductance Amplifiers (OTAs) and
several passive components, [8]; circuit structure is shown in Figure 2.6.
30
Figure 2.6: MC-MR mutator circuit by Biolek et al.
In 2010 Biolek et al. using one plus type Second Generation Current Conveyor
(CCII+) and one OTA proposed mutators which mutate memristors into memca-
pacitors and meminductors. The proposed metamutator realization is shown in
Figure 2.7; the constitutive relation of the memristor is preserved, within scaling,
by the elements obtained after the mutation [9].
Figure 2.7: MC-MR mutator circuit by Biolek et al.
In 2011 Pershin and Ventra, using four current conveyors (CCII) and several pas-
sive elements mutated a memristor to a floating memcapacitor or a meminductor.
The circuit implementation is shown in Figure 2.8.
In the same paper, with two dual output current conveyors and several passive
components, they proposed other circuits for emulating a floating meminductor
and a memcapacitor from a memristor [11]. The circuit structure of these muta-
tors are shown in Figure 2.9.
31
Figure 2.8: CCII based meminductor, memcapacitor emulators [11]
Figure 2.9: Meminductor and memcapacitor emulation with dual-output CCII
32
Chapter 3
4-Port Metamutators and Their Realizations
3.1 Incognito Presence of Metamutators in Literature
Many electrical circuits, especially those used in realizing emulators/simulators,
gyrators, mutators etc. contain, concealed in their complex structure, a sub-
circuit which viewed as a 4-port behaves like a Metamutator. Nobody has been
able to identify this underlying 4-port and its ability to act as a Metamutator,
let alone their diverse applications. In this chapter in addition to introducing
some of these incognito metamutator realizations, newly designed metamutator
circuits will be presented.
3.1.1 CCII+, CCII- Based Metamutator
In 1970, several new applications of current conveyors were investigated by Sedra
and Smith. The circuit shown in Figure 3.1 was introduced in [22] to operate as
a gyrator for realizing a grounded inductor.
In the following it will be shown that the 4-port given in Figure 3.2 extracted
from the circuit shown in Figure 3.1, behaves like a metamutator by proving that
its port description satisfies the defining expression of CIM as given with (1.10).
In the circuit of Figure 3.2 one CCII+ and one CCII- are used. The block diagrams
and port description matrices of current conveyors are given below:
33
Figure 3.1: The gyrator circuit by Sedra and Smith [22]
Figure 3.2: Diagram of the metamutator obtained from the gyrator circuit in
[22].
Figure 3.3: Block diagram of CCII+
      iy 0 0 0 vy     vx = 1 0 0×  ix  (3.1)
iz 0 1 0 vz
34
Figure 3.4: Block diagram of CCII-
      iy  0 0 0  vy     vx = 1 0 0 × ix  (3.2)
iz 0 −1 0 vz
CMOS realization of CCII+ and CCII- extracted from [23] are shown in Figure
3.5.
Transistor dimensions are given with Table 3.1 and Table 3.2.
MOSFET W (µm) L (µm)
M1, M2, M3 50 1.05
M7, M8 40 1.05
M9 120 1.05
M10, M11, M12, M13 20 1.05
Table 3.1: Dimension of transistors used in CCII+
MOSFET W (µm) L (µm)
M1, M2, M4 50 1.05
M5, M6, M7, M8 40 1.05
M9 120 1.05
M10, M11, M12, M14, M15, M16 20 1.05
Table 3.2: Dimension of transistors used in CCII-
By applying KVL, KCL and writing a chain of equalities from the description
matrices of CCII+ and CCII-, port relation matrix of the 4-port in Figure 3.2 is
obtained as:
35
Figure 3.5: CMOS realization of: (a) (CCII+), (b) (CCII-)

 i2 
 
 
  
 i4  
1 0 0 0  
i3 
 0 1 0 0  −i1   =  × v3 0 0 1 0  v4  (3.3)
v1 0 0 0 1 v2
As one can see the port relation matrix of the 4-port in Figure 3.2 is the same
as (1.10), which verifies that the configuration in Figure 3.2 is indeed a CIM.
Comparing with (1.9) that m = 3, l = 4, n = 1 and k = 2 can be observed.
In the following, the frequency ranges in which the CCII+, CCII- metamutator’s
36
port relations in (3.3) are satisfied, will be investigated. For CCII+ and CCII-,
TSMC, 0.35 µm CMOS process parameters were used with transistor dimensions
as shown in Table 3.1 and Table 3.2 and their circuits given in Figure 3.5. Supply
voltages are chosen as ±1.65V, and VB as 0.7V.
Figure 3.6: Theoretical and simulation characteristics of i4 vs. i1
The characteristic in Figure 3.6 is obtained by applying an AC current source
with amplitude of 10µA to port 1 and connecting 1Ω resistors to other ports of
the metamutator.
Figure 3.7: Theoretical and simulation characteristics of i3 vs. i2
The characteristic in Figure 3.7 is achieved by applying an AC current source
with amplitude of 10µA to port 2 and connecting 1Ω resistors to the other ports
37
of the metamutator. According to simulation results in Figure 3.6 and Figure
3.7, currents match up until 100+MHz which proves that the operation of this
metamutator is as desired in a wide range of frequency.
Figure 3.8: Theoretical and simulation characteristics of v2 vs. v1
The characteristic in Figure 3.8 is achieved by applying an AC voltage source
with 1V amplitude to port 2 and connecting 100kΩ resistors to the other ports
of the metamutator.
Figure 3.9: Theoretical and simulation characteristics of v3 vs. v4
The characteristic in Figure 3.9 is achieved by applying an AC voltage source
with 1V amplitude to port 4 and connecting 100kΩ resistors to the other ports
of the metamutator.
38
According to simulation results in Figure 3.8 and Figure 3.9, voltages match up
until 50+MHz proving the operation of the metamutator is as desired in a wide
range of frequency.
3.1.2 CCII+ and CF Based Metamutator
Another metamutator circuit structure is shown in Figure 3.10. A plus type
second generation Current Conveyor (CCII+) and a Current Follower (CF) are
employed in the structure of this metamutator.
Figure 3.10: Metamutator with CCII+ and CF [27]
First the circuit was present in a configuration built for realizing grounded or
floating inductors in [27] but definitely not as a metamutator. Then in [24-26]
the circuit was slightly modified for realizing a metamutator. The port diagram
and port description matrix of the current follower are given below:
Figure 3.11: Block diagram of CF
39
 vx 
  
 0
iz+   =  1  .ix (3.4)
iz− −1
The CMOS realization of CF extracted from [23] is shown with Figure 3.12
Figure 3.12: CMOS realization of CF
Transistor dimensions are shown in Table 3.3.
MOSFET W (µm) L (µm)
M1, M2,M3, M4 50 1.05
M5, M6, M7, M8 40 1.05
M9 120 1.05
M10, M11, M12, M13, M14, M15, M16 20 1.05
Table 3.3: Dimension of transistors used in CF
By writing Kirchoff’s laws and applying chain of defining equalities (3.1) and
(3.4) for CCII+ and CF based metamutator in Figure 3.10, the matrix equality
(3.5) is obtained,
     

i1 
 1 0 0 0  i3 i2  0 1 0 0 i4  v3  =  ×   (3.5)0 0 1 0 v2 
v4 0 0 0 1 −v1
40
As one can see the ports relation matrix of 4-port with CCII+ and CF+ is
the same as (1.9), so this is a VIM configuration. Comparing with (1.9) gives,
m = 3, l = 2, n = 4 and k = 1.
In the sequel the frequency ranges in which CCII+ and CF based metamutator
operates optimally have been investigated. For CCII+ and CF TSMC, 0.35 µm
CMOS process parameters were used with transistor dimensions as shown in
Table 3.1 and Table 3.3, their circuit in Figure 3.5 (a) and Figure 3.12 and,
supply voltages chosen as ±1.65V, and VB as 0.7V.
Figure 3.13: Theoretical and simulation characteristics of i1 vs. i3
The characteristic in Figure 3.13 is achieved by applying an AC current source
with amplitude of 100µA to ports 3 and connecting 1Ω resistors to the other ports
of CCII+ and CF based metamutator.
The characteristic in Figure 3.14 is achieved by applying an AC voltage source
with amplitude 100µA to ports 4 and connecting 1Ω resistors to the other ports
of CCII+ and CF based metamutator.
According to simulation results in Figure 3.13 and Figure 3.14, currents match
up until 80MHz and 60MHz respectively, which prove the proper operation of
CCII+ and CF based metamutator is as desired in a wide range of frequency.
41
Figure 3.14: Theoretical and simulation characteristics of i2 vs. i4
Figure 3.15: Theoretical and simulation characteristics of v4 vs. v1
The characteristic in Figure 3.15 is achieved by applying an AC voltage source
with amplitude of 1V to port 1 and connecting 100kΩ resistors to the other ports
of CCII+ and CF based metamutator.
The characteristic in Figure 3.16 is achieved by applying an AC voltage source
with amplitude of 1V to port 2 and placing 100kΩ resistors to the other ports of
CCII+ and CF based metamutator.
According to simulation results in Figure 3.15 and Figure 3.16, voltages match up
until 20MHz for both characteristics which prove the operation of metamutator
42
Figure 3.16: Theoretical and simulation characteristics of v3 vs. v2
with CCII+ and CF is as desired in a wide range of frequency.
3.1.3 CCII+ Based Metamutator
The circuit in Figure 3.17 was first introduced by Ferri for the purpose of simu-
lating a floating inductor [82].
Figure 3.17: CCII+ based inductor simulator proposed in [82]
43
In the following it will be shown that the 4-port given in Figure 3.18 extracted
from the circuit shown in Figure 3.17, behaves like a metamutator by proving
that its port description satisfies the defining expression of VIM as given in (1.9).
Figure 3.18: Diagram of metamutator extracted from [82]
In the circuit of Figure 3.18 four plus type second generation current conveyors
are used. The block diagram and port description matrix of the current conveyor
are presented in Figure 3.3 and (3.1).
By applying KVL, KCL and writing a chain of equalities from the description
matrix of CCII+, port relation matrix of the 4-port in Figure 3.18 will be obtained
as:
      i4 
 
 
1 0 0 0 i1
 
   

 i2  0 1 0 0 i   =  × 
3
  (3.6)v1 0 0 1 0 −v2 
v3 0 0 0 1 v4
As one can see the ports relation matrix of the meminductor simulator configu-
ration in [82] is the same as (1.9) which verifies that the configuration in Figure
3.18 is indeed a VIM. Comparing with (1.9), m = 3, l = 4, n = 1 and k = 2 is
observed.
44
In the following, the frequency ranges in which CCII+ based metamutator oper-
ates optimally is investigated. For CCII+ TSMC, 0.35µm CMOS process param-
eters were used with transistor dimensions as shown in Table 3.1 and its circuit
as in Figure 3.5 (a). supply voltages chosen as ±1.65V, and VB as 0.7V.
Figure 3.19: Theoretical and simulation characteristics of i2 vs. i3
The characteristic in Figure 3.19 is obtained by applying an AC current source
with amplitude of 100µA to port 3 and connecting 1Ω resistors to the other ports
of CCII+ based metamutator.
Figure 3.20: Theoretical and simulation characteristics of i1 vs. i4
The characteristic in Figure 3.20 is achieved by applying an AC current source
with amplitude of 100µA to port 1 and connecting 1Ω resistors to the other ports
of CCII+ based metamutator.
45
According to Simulation results in Figure 3.19 and Figure 3.20 currents match
up until 100MHz and 30MHz respectively which prove the operation of CCII+
based metamutator is as desired in a wide range of frequency.
Figure 3.21: Theoretical and simulation characteristics of v3 vs. v4
The characteristic in Figure 3.21 is achieved by applying an AC voltage source
with amplitude of 1V to port 4 and replacing 100kΩ resistors in the other ports
of CCII+ based metamutator.
Figure 3.22: Theoretical and simulation characteristics of v2 vs. v1
The characteristic in Figure 3.22 is achieved by applying an AC voltage source
with amplitude of 1V to port 2 and connecting 100kΩ resistors to the other ports
of CCII+ based metamutator.
46
According to simulation results in Figure 3.21 and Figure 3.22, voltages match
up until 300MHz and 70MHz respectively which prove the operation of CCII+
based metamutator is as desired in a wide range of frequency.
3.1.4 Adder and Subtractor Metamutator
Another metamutator configuration is shown in Figure 3.23. As one can see
one adder and one subtractor blocks are used in the structure of this circuit.
The circuit first was introduced in [4] for realizing a memristor but, not called a
metamutator and then in [24-26], it was modified for the purpose of obtaining a
4-port metamutator.
Figure 3.23: Generalized 4-port mutator with adder and subtractor [24-26]
Ideal block diagrams and port relations of adder and subtractor are shown in Fig.
3.24 (a) and (b) respectively,
By writing Kirchoff’s laws and applying chain of equalities using the port relations
of Adder and Subtractor in Figure 3.23, the matrix equality (3.7) is obtained,
47
Figure 3.24: Block diagrams and defining relations of (a) adder, (b) subtractor.
      i3  1 0 0 0 i1 i4  
  
0 1 0 0  =   
 i× 2  (3.7)
v1 0 0 1 0  v4 
v2 0 0 0 1 −v3
As one can see the ports relation matrix of 4-port with Adder and Subtractor is
the same as (1.9), so this is a VIM configuration. Comparing with (1.9) gives, m =
1, l = 4, n = 2 and k = 3. Next, the frequency range in which the metamutator
with adder and subtractor operates as defined with (3.7) is investigated. As adder
and subtractor circuits the CMOS realization with 0.25µm technology with the
same transistor dimensions and supply voltages introduced in [4] are used.
The characteristic in Figure 3.25 is achieved by applying an AC current source
with amplitude of 10µA to ports 2 and connecting 1Ω resistors to the remaining
ports of metamutator with adder and subtractor.
The characteristic in Figure 3.26 is reached by applying an AC current source
with amplitude of 10µA to ports 2 and connecting 1Ω resistors to the other ports
of metamutator with adder and subtractor.
48
Figure 3.25: Theoretical and simulation characteristics of i3 vs. i1
Figure 3.26: Theoretical and simulation characteristics of i4 vs. i2
According to simulation results in Figure 3.25 and Figure 3.26, currents match
up until 2THz and 1GHz respectively which prove the operation of metamutator
with adder and subtractor is as desired in a wide range of frequency.
The characteristic in Figure 3.27 is reached by applying an AC voltage source
with amplitude of 1V to ports 1 and attaching 100kΩ resistors to the other ports
of metamutator with adder and subtractor.
The characteristic in Figure 3.28 is obtained by applying an AC voltage source
with amplitude of 1V to ports 2 and connecting 100kΩ resistors to the other ports
of metamutator with adder and subtractor.
49
Figure 3.27: Theoretical and simulation characteristics of v4 vs. v1
Figure 3.28: Theoretical and simulation characteristics of v3 vs. v2
According to simulation results in Figure 3.27 and Figure 3.28 voltages match up
until 20MHz and 100MHz respectively which prove the operation of metamutator
with adder and subtractor is as desired in a wide range of frequency.
3.2 New Designs for Metamutators with Two Active Devices
In this section three newly designed metamutators using two active blocks each,
are being proposed.
50
3.2.1 Realization with One CFOA and One CCII+
The first metamutator configuration is built using one Current Feedback Opera-
tional Amplifier (CFOA) and one second-generation plus type Current Conveyor
(CCII+) as illustrated in Figure 3.29.
Figure 3.29: Metamutator using CFOA and CCII+
The port definition of ideal CCII+ and CFOA elements are given with matrix
representations as shown in (3.8) and (3.9) respectively.
   
iy  0 0 0  
 
 vy 
vx = 1 0 0×  ix  (3.8)
iz 0 1 0 vz
     
iz 1 0 0

 vx   = 
 ix
0 1 0 ×
 vy  (3.9)vw 0 0 1
vz
iy 0 0 0
The following chain of equalities is obtained using port descriptions of CFOA and
CCII+ and applying Kirchoff’s Laws
51
v2 = v(x1) = v(y1) = v3 → v2 = v3
v1 = v(z1) = v(w1) = v4 − v(x2) = v4 − v(y2) → v4 = v1
i2 = i(x1) = i(z1) = i1 → i1 = i2
i3 = i(z2) = i(x2) = −i4 → i3 = −i4
So the ports description matrix of Figure 3.29 is obtained as,
      i1  1 0 0 0 i2


i3 
   = 0 1 0 0 × 
 
 −i4   (3.10)v2 0 0 1 0 v3
v4 0 0 0 1 v1
Comparison with (1.9) verifies the existence of CIM configuration. In this case
n = 4, l = 3,m = 2 and k = 1.
3.2.2 Realization with Two DOCCII
The second metamutator configuration is designed by using two Dual Output
Current Conveyors (DOCCII) as illustrated in Figure 3.30.
Figure 3.30: Metamutator with two DOCCIIs
The port definition of ideal DOCCII element is given with the matrix represen-
tation shown in (3.11),
52
  i 

 

1 0 0   z+ ix iz−  −1 0 0  =  
 
×  vy  (3.11)vx 0 1 0 vz
iy 0 0 0
Again, the relation between currents and voltages of the ports in the circuit of
Figure 3.30, after some algebraic manipulations becomes as given with expression
(3.12).
      i4 
 1 0 0 0 i3 i2  
  
 0 1 0 0  =  × 


i1 
v3 0 0 1 0   (3.12)v2 
v1 0 0 0 1 −v4
Comparison with (1.9) confirms the existence of VIM configuration. In this case
n = 1, k = 4, l = 2 and m = 3.
3.2.3 Realization with Two CFOA
The third metamutator is designed by using two Current Feedback Operational
Amplifiers (CFOA) as illustrated in Figure 3.31.
Figure 3.31: Metamutator realized with two CFOAs
53
The port definition of ideal CFOA element is given with the matrix representa-
tion as shown in (3.9). Again, after some algebraic manipulations the relations
between currents and voltages of the ports in metamutator shown in Figure 3.31,
become as given with expression (3.13).
      i1 
 
 i3 
1 0 0 0  i2    0 1 0 0  −i4  = ×  (3.13)v2  0 0 1 0  v3 
v4 0 0 0 1 v1
Comparing with (1.10) verifies the existance of CIM configuration. In this case
n = 4, k = 1, l = 3 and m = 2.
3.3 New Designs of Metamutators with Single Active Device
In this chapter three newly proposed metamutator configurations employing only
one active devices will be presented. By properly interconnecting the terminals of
active devices a Metamutator will be obtained without use of any other external
element.
It maintains the following advantages:
i. Use of only one active element, less is the number of active devices less is the
amount of disparity
ii. Possibility of realizing Capacitors, Inductors, Memristors, Frequency Depen-
dent Negative Resistor (FDNR), which can be used to make integrated cir-
cuits and active filters
iii. No need to impose component choice constraints.
54
3.3.1 Realization with Negative Type Fully Differential Current Con-
veyor (FDCCII-)
One of the newly proposed Metamutator configurations employs only one Nega-
tive Type Fully Differential Current Conveyor (FDCCII-) which has 9 terminals
including ground. By properly interconnecting the terminals of FDCCII- two dif-
ferent types of Metamutator will be obtained without use of any other external
element.
The block diagram of the FDCCII- is shown in Figure 3.32.
Figure 3.32: Block diagram of FDCCII-
The port description matrix of FDCCII- is,
   
 ixp 
 vxp 
  0 0 1 −1 1 0  ixn 

vxn  
   
 = 
0 0 −1 1 0 1  v × 
y1  (3.14)
izp −1 0 0 0 0 0  vy2 
izn 0 1 0 0 0 0  vy3 
vy4
And iy1 = iy2 = iy3 = iy4 = 0.
55
The CMOS realization of FDCCII- extracted from [84] is shown below.
Figure 3.33: CMOS realization of FDCCII- [84]
MOSFET W (µm) L (µm)
M1, M2,M4, M5, M6 0.7 8.75
M7, M8, M9, M13 0.7 70
M10, M11, M12, M24 0.7 17.5
M14, M15,M18, M19, M25, M29, M30,M33, M34, M37, M38 0.35 35
M16, M17,M20, M21, M26, M31, M32,M35, M36, M39, M40 0.35 8.75
M22, M23, M27, M28 0.7 0.7
Table 3.4: Dimension of transistors used in FDCCII-
With proper interconnections of port branches as shown in Figure 3.34 and Figure
3.35 two different realizations of metamutators, one CIM type and the other VIM
type, are achieved.
By connecting ports y1 and y2 of FDCCII- in Figure 3.32 to ground and applying
proper interconnections to other ports the metamutator in Figure 3.34 will be
observed.
According to (3.14) the ports description matrix of metamutator will become as,
56
Figure 3.34: CIM type metamutator realized with single FDCCII-
    i1  
1 0 0 0  i2 
 i3  0 1 0 0  =  
  − i ×  4  (3.15)
v2 0 0 1 0  v3 
v4 0 0 0 1 v1
Comparing with (1.10) verifies the existence of CIM type configuration. In this
case n = 4, k = 1, l = 3 and m = 2.
In Figure 3.32, by connecting the ports y2, Zp and Zn of FDCCII- to ground and
applying proper interconnections to other ports the metamutator in Figure 3.35
will be achieved.
According to (3.15) the ports description matrix of metamutator will become as,
     
i1 
 i3  
1 0 0 0  i2 
 = v2  
0 1 0 0  i ×  4
0 0 1 0  v3  (3.16)
v4 0 0 0 1 −v1
Comparing with (1.9) verifies the existence of VIM type metamutator configura-
tion. In this case n = 4, k = 1, l = 3 and m = 2.
57
Figure 3.35: VIM type metamutator realized with single FDCCII-
As the ports description matrix of these newly proposed metamutators are the
same as (1.9) and (1.10), the Table 1.3 stands true for these two metamutators.
In the sequel, frequency ranges in which metamutator realized with single FDCCII-
shown in Figure 3.34 operates properly have been investigated. For FDCCII-
TSMC, 0.18µA CMOS process parameters were used with transistor dimensions
as shown in Table 3.4 and its circuit in Figure 3.5 (a) and Supply voltages are
chosen as ±0.9V, Vbp = Vbn = 0V and IB = ISB = 50µA.
Figure 3.36: Ideal and non-ideal gain of i1 and i2
58
The characteristic in Figure 3.36 is achieved by applying an AC current source
with amplitude of 100µA to port 1 and replacing 1Ω resistors in the other ports
of FDCCII- based metamutator.
Figure 3.37: Ideal and non-ideal gain of i2 and i3
The characteristic in Figure 3.37 is achieved by applying an AC current source
with amplitude of 100µA to port 3 and replacing 1Ω resistors in the other ports
of FDCCII- based metamutator.
According to Simulation results in Figure 3.36 and Figure 3.37, currents match
up until 1GHz and 200MHz respectively which prove the operation of FDCCII-
based metamutator in a wide range of frequency as desired.
Figure 3.38: Ideal and non-ideal gain of v2 and v3
59
The characteristic in Figure 3.38 is achieved by applying an AC voltage source
with amplitude of 1V to port 3 and replacing 100kΩ resistors in the other ports
of FDCCII- based metamutator.
Figure 3.39: Ideal and non-ideal gain of v4 and v1
The characteristic in Figure 3.39 is achieved by applying an AC voltae source
with amplitude of 1V to port 1 and replacing 100kΩ resistors in the other ports
of FDCCII- based metamutator.
According to Simulation results in Figure 3.38 and Figure 3.39, currents match
up until 100kHz and 1.5GHz respectively which prove the operation of FDCCII-
based metamutator in a wide range of frequency as desired.
3.3.2 Realization with Dual X Current Conveyor (DXCCII)
Another newly proposed metamutator configuration employs only one Dual X
Current Conveyor (DXCCII) which has 6 terminals including ground. By properly
interconnecting the terminals of DCCII a metamutator will be obtained without
usage of any other external elements.
The schematic block diagram of active element DCCII is shown in Figure 3.40
The port description matrix of DCCII is,
60
Figure 3.40: Schematic block diagram of DXCCII
      vxp  1 0 0 0 0  vy 

  vxn   1 0 0 0 0  ixp 
 izp  = 0 1 −1 0 0×  izn   −  0 1 1 0 0 
ixn
vzp 
 (3.17)

iy 0 0 0 0 0 vzn
The CMOS realization of DXCCII extracted from [83] are shown below.
Figure 3.41: CMOS realization of DXCCII
Transistor dimensions are shown in Table 3.5.
By applying proper interconnections between the ports of DXCCII the metamu-
tator configuration in Figure 3.42 will be achieved.
61
MOSFET W (µm) L (µm)
M1, M2,M4, M5, M6, M7, M8, M9, M10, M17, M18, M19, M20 20 1.05
M3 40 1.05
M11, M12,M13, M14, M15, M16 50 1.05
Table 3.5: Dimension of transistors used in DXCCII
Figure 3.42: Newly proposed metamutator with DXCCII
According to (3.17) the ports description matrix of metamutator in Figure 3.42
will become as,
 i1 
    
 1 0 0 0 

 

  
 i4 
v2 0 1 0 0  v1 
 =i3   ×   (3.18)0 0 1 0  i2 
v4 0 0 0 1 −v3
Comparing with (1.9) verifies the existance of VIM type metamutator so the
Table 1.3 stands true for this metamutator. In this case n = 4, k = 3, l = 1 and
m = 2.
In the following, the frequency ranges in which the DXCCII based metamutator’s
port relations in (3.18) are satisfied will be investigated. For DXCCII TSMC, 0.35
µm CMOS process parameters were used with transistor dimensions as shown in
Table 3.5 and its circuit in Figure 3.41, supply voltages are chosen as ±1.65V,
and VB as 0.7V.
62
Figure 3.43: Ideal and non-ideal gain of i1 and i4
The characteristic in Figure 3.43 is achieved by applying an AC current source
with amplitude of 100µA to port 4 and replacing 1Ω resistors in the other ports
of DXCCII based metamutator.
Figure 3.44: Ideal and non-ideal gain of i3 and i2
The characteristic in Figure 3.44 is achieved by applying an AC current source
with amplitude of 100µA to port 2 and replacing 1Ω resistors in the other ports
of DXCCII based metamutator.
According to Simulation results in Figure 3.43 and Figure 3.44, currents match up
until 1MHz and 1THz respectively which prove the operation of DXCCII based
metamutator in a wide range of frequency as desired.
63
Figure 3.45: Ideal and non-ideal gain of v2 and v1
The characteristic in Figure 3.45 is achieved by applying an AC voltage source
with amplitude of 1V to port 1 and replacing 100kΩ resistors in the other ports
of DXCCII based metamutator.
Figure 3.46: Ideal and non-ideal gain of v4 and v3
The characteristic in Figure 3.46 is achieved by applying an AC voltage source
with amplitude of 1V to port 3 and replacing 100kΩ resistors in the other ports
of DXCCII based metamutator.
According to Simulation results in Figure 3.45 and Figure 3.46 voltages match
up until 160MHz and 40MHz respectively which prove the operation of DXCCII
based metamutator in a wide range of frequency as desired.
64
3.3.3 Realization with Newly Designed AD-IC
The block diagram of newly designed Additive and Differential Integrated Cir-
cuit (AD-IC), built only with twelve transistors which has 5 terminals including
ground. The schematic block diagram and ports description matrix of AD-IC are
shown in Figure 3.47 and (3.19) respectively.
Figure 3.47: Schematic block diagram of AD-IC
      vx1  1 −1 0 0 vy1 vx2  
  
1 1 0 0
  =  

×  vy2
iy1 0 0 0 0  ix1 
 (3.19)
iy2 0 0 0 0 ix2
In the realization of AD-IC, TSMC 0.25µm CMOS process parameters are used,
with transistor dimensions as shown in Table 3.6 and its circuit structure in Figure
3.48.
MOSFET W (µm) L (µm)
M1, M2,M5, M6, M7, M8, M9, M10 1 0.5
M11, M12,M13, M14 30 0.5
Table 3.6: Dimension of transistors used in AD-IC
The developed layout of the AD-IC circuit of Figure 3.48 is shown in Figure
3.49 The area of the AD-IC is calculated to be approximately 60X22µm2.Post-
layout simulations are performed with the parameters extracted from the layout
netlist using TSMC 0.25µm process technology. The supply voltages are taken
as ±1.25V forVDD,VSS and 0.8V for VB.
65
Figure 3.48: The implementation of AD-IC with twelve MOS transistors
Figure 3.49: Layout of the AD-IC circuit
The equivalent parasitic capacitance CL at the output terminal is approximately
73fF. The W/L ratios of the output node transistors M3, M4, M11 and M12 in
Figure 3.48 are chosen much larger than the ratio of other transistors for the
purpose of providing a smaller output resistance.
With proper interconnections of port branches as shown in Figure 3.50 a new
realization of metamutators will be achieved.
66
Figure 3.50: Schematic diagram of metamutator with AD-IC
According to (3.19) the ports description matrix of metamutator in Figure 3.50
will become as,
     
i4  1 0 0 0 i3 i2 
  
 

0 1 0 0  

i1 
 v3  =  ×0 0 1 0   (3.20)v2 
v1 0 0 0 1 −v4
Comparing with (1.9) verifies the existance of VIM type configuration so the
Table 1.3 stands true for this metamutator. In this case n = 1, k = 4, l = 2 and
m = 3. In continue the frequency range in which the AD-IC based metamutator
operates optimally is investigated.
The characteristic in Figure 3.51 is achieved by applying an AC current source
with amplitude of 100µA to port 4 and replacing 1Ω resistors in the other ports
of AD-IC based metamutator.
The characteristic in Figure 3.52 is achieved by applying an AC current source
with amplitude of 100µA to port 2 and replacing 1Ω resistors in the other ports
of AD-IC based metamutator.
67
Figure 3.51: Ideal and non-ideal gain of i3 and i4
Figure 3.52: Ideal and non-ideal gain of i1 and i2
According to Simulation results in Figure 3.51 and Figure 3.52, currents match
up until 5GHz in both of them which prove the operation of AD-IC based meta-
mutator in a wide range of frequency as desired.
The characteristic in Figure 3.53 is achieved by applying an AC voltage source
with amplitude of 1V to port 2 and replacing 100kΩ resistors in the other ports
of AD-IC based metamutator.
The characteristic in Figure 3.54 is achieved by applying an AC voltage source
with amplitude of 1V to port 4 and replacing 100kΩ resistors in the other ports
of AD-IC based metamutator.
68
Figure 3.53: Ideal and non-ideal gain of v3 and v2
Figure 3.54: Ideal and non-ideal gain of v4 and v1
According to simulation results in Figure 3.53 and Figure 3.54, voltages match up
until 40MHz and 30MHz which prove the operation of AD-IC based metamutator
in a wide range of frequency as desired.
The frequency ranges in which incognito metamutators in the literature and the
newly designed metamutators with Single Active Devices operate optimally are
comparised and shown in Table 3.7.
Also a general comparison between all types of mutators is given in Table 3.8.
69
Metamutator Frequency Frequency # of
Realization Range for Op- Range for Op- Tran-
timal Current timal Voltage sis-
Ratio Ratio tors
CCII+, CCII- 100 MHz 30 MHz 32
Adder/ Subtractor 2THz 1GHz 20MHz 100MHz 12
In literature
CCII+, CF 80MHz 60MHz 20MHz 26
2 CCII+ 100MHz 30MHz 300MHz 70MHz 40
FDCCII- 1GHZ 200MHz 100KHz 1.5GHz 32
Here DXCCII 1MHz 1THz 160MHz 40MHz 20
AD-IC 1GHZ 40MHz 30MHz 12
Table 3.7: Comparison between frequency range for optimal operation of
incognito metamutators in literature and newly designed of metamutators
70
Table 3.8: General comparison between all types of mutators
71
Chapter 4
Different Applications of Metamutators
In this chapter, applications of metamutators developed during the research pe-
riod of this thesis will be presented. As the port description matrix of all intro-
duced metamutators in chapter 3 are the same as (1.9) for VIM type and (1.10)
for CIM type metamutators, all of the applications in this chapter stand true for
all of metamutators. Depending on how some of the ports are terminated, many
metamutator applications, which can be classified in two groups, will be attained:
I. 1-port circuits realized with metamutators,
II. 2-port circuits realized with metamutators.
In 1-port realizations, by properly terminating three ports of the metamutator
the resulting circuit will behave as the desired 2-terminal element at the fourth
port. A list of so realizable 2-terminal elements is depicted with Table 1.3.
In 2-port realizations, by properly terminating two metamutator ports the result-
ing circuit will behave as the desired 2-port from the remaining two ports. A list
of so realizable 2-ports is given with Table 4.5.
These applications will be examined in detail with PSPICE simulations using
transistor parameters obtained from layout level descriptions of metamutators
and comparison between simulation results and theoretical results will be demon-
strated in sections 4.1 and 4.2 realizations of 1-Port.
72
4.1 Realization of 1-ports
4.1.1 Mutating Nonlinear Resistor to Memristor
To illustrate the working principle of the metamutator as a memristor mutator,
the realization in row #12 of Table 1.3 has been applied to the metamutator with
AD-IC. By terminating ports 3, 4 and 2 of the metamutator in Figure 3.50 with
a nonlinear resistor, inductor and capacitor respectively a memristor is obtained
at port 1. The circuit structure is shown in Figure 4.1.
Figure 4.1: Memristor realization with AD-IC based metamutator
The nonlinear-resistor modeled by the circuit presented in [26] and shown in
Figure 4.2 is used.
Figure 4.2: Implementation on non-linear load of M-R mutators.
The port analysis of this circuit is as follow. Let the definition of the nonlinear-
resistor at port 3, with the assigned polarities, be given by (4.1),
73
f(i3,−v3) = 0 (4.1)
Replacing i3 with i4 and v3 with v2 according to (3.20), gives:
f(i4,−v2) = 0 (4.2)
Use of the elements’ constitutive relations i4 = −ϕ4/L and −v2 = q2/C in (1.10)
results in,
−ϕ4 q2
f( , ) = 0 (4.3)
L C
Finally, use of (3.20) again to replace ϕ4 and q2 by −ϕ1 and q1 respectively, yields
(4.4) which is a memristor constitutive relation with the same characteristic,
within scaling factors L and C, as the nonlinear resistor in Figure 4.1. In order for
expression (4.4) to conform with expression (4.1) the polarities of the memristor
so obtained should have the same relative position.
ϕ1 q1
f( , ) = 0 (4.4)
L C
By comparing (4.4) and (2.4), the scaling factors Kx = C and Ky = L can be
verified.
Selecting a sinusoidal voltage source with amplitude 3.5V and frequency of 30 Hz
at port 4 of the metamutator in Figure 4.1, the current versus voltage characteris-
tic has been obtained as shown in Figure 4.3. For the nonlinear resistor the model
shown in Figure 4.2 and for AD-IC TSMC, 0.25µm CMOS process parameters
are used with transistor dimensions as shown in Table 3.6 and its circuit in Fig-
ure 3.48. Supply voltages are chosen as ±1.25V, VB = 0.8V. The capacitor and
74
Figure 4.3: i− v characteristic of memristor
inductor values were selected as 0.1nF and 2.5mH, respectively. The Lissajous
curve in Figure 4.1 confirms the signature of a memristor at port 4.
4.1.2 Mutating Memristor to Meminductor
To illustrate the working principle of the metamutator as meminductor mutator,
the metamutator structure in Figure 3.10 is chosen. By terminating ports 2, 3, 4
of the metamutator with capacitor, memristor and resistor respectively, according
to row #4 of Table 1.3, the circuit in Figure 3.10 becomes as shown in Figure 4.4
and a meminductor results at port 1.
Figure 4.4: Meminductor realization with memristor terminated metamutator
The port analysis of this circuit is as follows: the definition of memristor at port
3 is,
75
f(q3,−ϕ3) = 0 (4.5)
Replacing q3 and ϕ3 by q1 and ϕ2 respectively according to (3.5) gives,
f(q1,−ϕ2) = 0 (4.6)
Using the element constitutive relation v2 = −q2/C at port 2 then taking the
integral of both hand sides gives ϕ2 = −σ2/C and replacing σ2 by σ4 to (4.6)
gives,
σ4
f(q1, ) = 0 (4.7)
C
Finally, as v4 = −R.i4 implies ρ4 = −R.σ4 and σ4 = −ρ4/R Replacing ρ4 by −ρ1,
yields the meminductor’s constitutive relation shown with (4.8),
ρ1
f(q1, ) = 0 (4.8)
RC
By comparing (4.8) and (2.16) the scaling factors Kx = RC and Ky = 1 can be
deduced. The PSPICE simulation result given in Figure 4.5 confirms very well
the signature of a meminductor.
The circuit in Figure 4.4 is simulated by placing a sinusoidal current source to
port 1 with amplitude and frequency of 10mA and 20Hz. For the memristor,
the HP model with parameter values of µ = 10(−10).cm2.s(−1).v(−1)v , Ron=10Ω,
Roff=20kΩ, Rinit=5kΩ, and as window function the Joglekar’s model [28] f(x) =
1–(2x–1)2p with p=10, for CF and CCII+, 0.13µm CMOS technology parameters
have been used. The transistor level circuits are shown in Figure 3.5 and Figure
3.12, parameters being given in Table 3.1 and Table 3.3 respectively; supply
76
Figure 4.5: ϕ− i characteristic of meminductor
voltages are selected as ±0.75V, VB = 0.24V and resistor and capacitor values as
1kΩ and 1nF, respectively.
4.1.3 Mutating Memristor to Memcapacitor
To illustrate the working principle of the metamutator, as memcapacitor muta-
tor , according to realization in row #5 of Table 1.3, ports 2, 3 and 4 of the
metamutator in Figure 3.2 are terminated with memristor, inductor and resistor
respectively. The circuit becomes as shown in Figure 4.6 and a memcapacitor is
obtained at port 1.
The port analysis of this circuit is as follows. The definition of memristor at port
2 is:
f(q2,−ϕ2) = 0 (4.9)
According to (3.3) replacing q2 and ϕ2 with q3 and ϕ1 respectively gives,
f(q3,−ϕ1) = 0 (4.10)
77
Figure 4.6: Memcapacitor realization with memristor terminated metamutator
Use of the elements’ of constitutive relations q3 = −ρ3/L and ρ3 = ρ4 = −R.σ4
so q3 = R.σ4/L as σ4 = −σ1 yields the memcapacitor’s constitutive relation in
(4.11).
f((R/L).σ1, ϕ1) = 0 (4.11)
By comparing (4.11) and (2.19), the scaling factorsKx = L/R and Ky = 1 are
observed. The PSPICE simulation result in Figure 4.7 confirms very well the
signature of a memcapacitor.
Circuit in Figure 4.7 is simulated by applying a sinusoidal voltage source to port
1 with an amplitude and frequency of 2V and 50Hz respectively. As memris-
tor the HP model with parameters Ron=1kΩ, Roff=100kΩ, Rinit=10kΩ, µv =
10(−10).cm2.s(−1).v(−1) and as window function, Joglekar’s model [28] f(x) =
1–(2x–1)2p with p=10 are used. As CCII+ and CCII- the CMOS realizations
with the same transistor parameters introduced in Chapter 3.1.1 were used. The
resistor and capacitor values were selected as 1kΩ and 10nF, respectively.
78
Figure 4.7: q − v characteristic of the memcapacitor
4.1.4 Floating and Grounded Impedance Scaling
In this section floating and grounded impedance scaling applications of the new
AD-IC based metamutator will be presented. By connecting impedances to three
of the ports, the impedance as seen from the remaining fourth port can be found
in terms of the connected ones as shown in Table 4.1. When reading column i of
Table 4.1 it should be understood that no element is connected to port i whereas
impedances Zj are connected to portj for j 6= i and i = n, l,m, k.
Figure 4.8: Metamutator terminated with port impedances
As an example assume i = n, in this case the other three ports are terminated
with Zl, Zm and Zk as illustrated in Figure 4.9.
79
Portn Portl Portm Portk
Type Floating Grounded Floating Grounded
Z Z = Zk .Z Z = Zmn l l .Zn Zm =
Zl .Z Z = Zn .Z
Zm Z k kk Zn Z lm
Table 4.1: Equivalent impedance at the ports
Figure 4.9: Port n of metamutator terminated with impedance Zn
After some algebraic manipulations using KCL and KVL and the port relation
matrix described in (3.20) , the impedance at the fourth port will be obtained as
in (4.12).
Figure 4.10: Impedance scaling calculated with signal flow-graph
− −1 − − → vn→ Zk.ZLvn = ( Zl). .( Zk).( 1).in Zn = Zn = (4.12)
Zm in Zm
An interesting conclusion that can be deduced from Table 4.1 is that the meta-
mutator allows the realization of grounded elements as well as floating ones.
80
4.1.4.1 Inductance Simulator
As coil realization of inductors on an integrated chip is highly undesirable many
inductor simulators have been proposed in the literature [29-30]. In this section
an application of metamutators as inductance simulator with a minimum number
of elements, only one active device AD-IC with 12 transistors, two resistors and
single capacitor, will be presented. According to Table 4.1 by properly connecting
one capacitor and two resistors to three of the ports, an inductor will result at
the fourth port. In this case the inductance value is equal to the product of the
values of capacitor and resistors. Four different realizations are shown in Table
4.2.
Realization Portn Portl Portm Portk Inductance
#1 Leq Rl Cm Rk Leq = CmRlRk
#2 Rn Leq Rm Ck Leq = CkRnRm
#3 Cn Rl Leq Rk Leq = CnRlRk
#4 Rn Cl Rm Leq Leq = ClRmRn
Table 4.2: Different realizations of inductor
To demonstrate an example, realization #2 of Table 4.2 will be considered. By
connecting Ck, Rn and Rm to three of the ports of the metamutator with AD-IC,
an inductor will be obtained at port l:
Zm.Zk Rm
Zl = = 1 .Rn = sCkRmRn→Lm = CkRmRn (4.13)Zn sCk
Equality (4.13) clearly confirms the existence of inductor at port l. Furthermore,
the performance of the proposed inductance is verified with the frequency response
plots of the actual and ideal inductor both given in Figure 4.11.
In this case the metamutator was simulated using an AC current source with
amplitude of 1mA. For AD-IC the CMOS realization with the same transistor
parameters introduced in subsection 3.3.3 was used. The values of resistors and
81
Figure 4.11: Phase and |impedance| plots of the inductor vs. frequency
capacitors have been selected as Rn = Rm = 1 kΩ and Ck = 25pF, which corre-
spond to an inductance of 25µH.
4.1.4.2 Capacitance Multiplier
In the design of integrated circuits, Capacitance Multipliers are being used for
the realization of large-valued capacitances on chip. The capacitance multiplier
can save valuable space on the chip in exchange for use of one active element and
two/three passive components. The final multiplied capacitance is larger than
one real on-chip capacitance, with smaller on-chip space required. In this section
an application of metamutator as capacitance multiplier, with minimum number
of elements and only one active device AD-IC with 12 transistors, is presented.
According to Table 4.1 by properly connecting one capacitor and two resistors to
three of the ports, a capacitor will be obtained at the fourth port. The different
realizations are shown in Table 4.3.
Applying realization in row #3 of the Table 4.3 to the metamutator with AD-IC
by connecting Cm, Rn and Rk to three of the ports of metamutator, a capacitor
with capacitance value of K.Cm will be obtained at port l. In this case K is the
ratio of resistors in the other two ports.
82
Realization Portn Portl Portm Portk Capacitance
#1 Ceq C
Cl.Rm
l Rm Rk Ceq = Rk
#2 Ceq Rl Rm Ck C =
Ck.Rm
eq Rl
#3 R C C R C = Cm.Rkn eq m k eq Rn
#4 C C R R C = Cn.Rkn eq m k eq Rm
#5 Rn Cl C R C =
Cl.Rn
eq k eq Rk
#6 R R C D C = Ck.Rnn l eq k eq Rl
#7 C R R Cn.Rln l m Ceq Ceq = Rm
#8 R R C C C = Cm.Rln l m eq eq Rn
Table 4.3: Capacitance multiplier realizations
1
Zm.Zk
Z = = sC
R
m k
l .Rn⇒Cl = Cm (4.14)
Zn Rk Rn
Equality (4.14) clearly confirms the existence of a capacitor in port l for which
the capacitance value is Cm.Rk/Rn . Moreover, the frequency response plots of
the multiplied capacitor and that of an ideal capacitor are given with Figure 4.12.
Figure 4.12: Phase and |impedance| plots of the capacitor vs. frequency
In this case the metamutator was simulated using an AC voltage source with
amplitude of 0.3V; For AD-IC the CMOS realization with the same transistor
parameters introduced in chapter 3.3.3 were used. The values of resistors and
capacitors have been selected as Rn= 1kΩ, Rk= 20kΩ and Cm= 5pF, which
corresponds to the value of multiplied capacitance of 100pF.
83
4.1.4.3 Frequency Dependent Negative Resistor Simulator
Low-pass filters have wide usage in radio frequency (RF) transceivers; in this
process the frequently used low-pass filter is called Anti-Aliasing Filter (AAF). By
reducing the size and refining the performance of these filters, new improvements
in communication are achieved. Figure 4.13 shows the position of AAF in fully
digital receivers.
Figure 4.13: Schematic of fully digital receiver [31]
As in general AAF are third or higher order passive LC ladder filters, using an
inductor in these circuits requires a lot of space and reduces the performance. In
order to decrease the size and improve the performance one can use the complex
impedance scaling technique for designing a prototype of the LC ladder circuits.
This technique, treated extensively by Bruton [32], is based on the fact that the
filter transfer function will remain unchanged if the impedance of each element is
divided by “s”. So the Inductor will be transformed into a resistor, the resistor
will be transformed into a capacitor and a capacitor will be transformed into a
Frequency Dependent Negative Resistor (FDNR).
By connecting two capacitors and one resistor to three of the ports, as detailed
in Table 4.1, a grounded or floating FDNR will be observed from the fourth port.
Different realizations and values of FDNRs are shown in Table 4.4.
It should be observed again that only twelve transistors and three passive elements
are being used with no component matching requirements.
84
Realization Portn Portl Portm Portk Capacitance
#1 D 1eq Cl Rm Ck Deq = s2ClCkRm
#2 Cn D
1
eq Cm Rk Deq = s2CnCmRk
#3 R 1n Cl Deq Ck Deq = s2ClCkRn
#4 Cn Rl C
1
m Deq Deq = s2CnCmRl
Table 4.4: FDNR realizations
Applying realization #4 to the metamutator with AD-IC as given in Table 4.4 and
connecting Cn, Rl and Cm to ports n, l and m of the metamutator respectively, a
FDNR will be observed from port k.
1
Zn.Zl
Z = = sC
1 1 1
n
k . = ⇒ D = − (4.15)
Z R sC s2
k 2
m l m CmCnRL w CmCnRl
Equality (4.15) clearly confirms the existence of FDNR in the fourth port. More-
over, the frequency domain phase and impedance characteristics of FDNR are
given in Figure 4.14.
Figure 4.14: Characteristics of FDNR in frequency domain
The metamutator with AD-IC was simulated using an AC voltage source with
amplitude of 1V. For AD-IC the CMOS realization with the same transistor
parameters introduced in chapter 3.3.3 was used. The values of Cn, Cm and Rl
were selected as 0.1nF, 0.2nF and 100kΩ, respectively.
85
4.1.5 RC-Oscillators
First quadrature feedback oscillator realization using metamutators was given in
[120]. Another new application of metamutator is its application as RC-oscillator.
The schematic block diagram of an RC oscillator is shown in Figure 4.15. By
applying this realization and selecting port l as output port, one can prove the
existence of an oscillator.
Figure 4.15: Block diagram of the RC-oscillator
Writing KVL and KCL the current at portk is,
ik = sCk(V0k − vk) (4.16)
and substituting circuit variables according to (3.20) gives,
vm vl
ik = sCk(V0k − vk) = im = − = − (4.17)
Rm Rm
After some algebraic manipulations expression (4.17) becomes as given with:
86
vl
sCkV0k + = sCkVk (4.18)
Rm
From the expression of the current for port l:
− − vn vk vkil = sClVl = in = = ⇒ sVl = − (4.19)
Rn Rn RnCl
is obtained, so (4.18) and (4.19) together give,
       sVl 0 − 1 V 0= ClRn×  l +   sV0k (4.20)
sV 1k 0 V 1C R kk m
Calculation of the determinant of the state matrix gives imaginary eigenvalues:
1
det(sI − A) = s2 + w 20 and w 20 = (4.21)
ClRnCkRm
It is well-known that the time-domain zero-input solution for Vout = Vl(s) is of
the form,
v(out) = a e
−jw0t
1 + a1e
−jw0t = 2|a1|cos(w0t+ ϕ) (4.22)
where|a1|ejϕ = a1. In caseRn = Rm = R and Ck = Cl = C one has an RC
oscillator with ω0 = 1/RC.
For a numerical application AD-IC based metamutator is selected and for obtain-
ing a sinusoidal waveform with frequency of 16kHz, the values of capacitors and
resistors were selected as Ck = Cl=10nf and Rn = Rm=1kΩ.
The output waveform resulting from the post layout simulation of the circuit in
Figure 4.15 is given in Figure 4.16. As for AD-IC, TSMC, 0.25µm CMOS process
parameters were used with transistor dimensions as shown in Table 3.6 and the
87
Figure 4.16: Simulation result of RC-oscillator
circuit in Figure 3.48. The supply voltages were chosen as ±1.25V and VB as 0.8
V.
4.2 Realization of 2-Ports
In 2-port realizations, by properly terminating two of the metamutator ports
the resulting circuit will behave as a desired 2-port from the remaining ports.
First such 2-port realizations were introduced in [120]. In the sequel, new 2-port
realizations will be given with a list, by no means complete, in Table 4.5.
4.2.1 Transconductance Amplifier
Another recent application of AD-IC based metamutator is its use in the design
of Transconductance Amplifiers which relates the output port current to the in-
put port voltage which was first given in [120] using Add-Subtract circuits. By
connecting one resistor and one AC voltage source (Vs) to two of the ports and
applying open circuit to the third port according to Table 4.5 the current in the
fourth port will be equal to the Vs multiplied by the conductance in the other
port.
88
Table 4.5: Different 2-port applications and realizations with metamutators
Applying realization #4 of Transconductance Amplifier in Table 4.5 to the meta-
mutator with AD-IC, connecting Vs and Rm to ports l and m respectively, apply-
ing an open circuit to port n of the metamutator, the circuit in Figure 4.17 will
89
be obtained,
Figure 4.17: Transconductance amplifier realization #4
In this case according to (3.20), the current in port k will be equal to Vs multiplied
by the conductance in port m as shown in:
− Vs ⇒ | | | ik 1ik = A = |= (f) (4.23)
Rm Vs Rm
Equality confirms the operation of the circuit in Figure 4.17 as a transconductance
amplifier; the frequency domain I/O characteristics are given in Figure 4.18.
The metamutator was simulated using an AC voltage source with amplitude of
1V. As for AD-IC, TSMC, 0.25µm CMOS process parameters were used with
transistor dimensions as shown in Table 3.6 and the circuit in Figure 3.48. The
supply voltages were chosen as±1.25V and VB as 0.8V. The values of Rk and Rm
were selected as 10Ω and 10KΩ respectively. It can be observed that the circuit
operates as transconductance amplifier for a wide range of frequency.
90
Figure 4.18: I/O characteristics vs. frequency of transconductance amplifier
4.2.2 Transimpedance Amplifier
Another recently proposed application of metamutators in [120] was the real-
ization, using Add-Subtract circuits, of a Transimpedance Amplifier. Here the
realization will be done using AD-IC based metamutator. By connecting one
resistor and one AC current source (Is) to two of the ports and applying open
circuit to the third port according to Table 4.5 the voltage in the fourth port will
be equal to Is multiplied by the impedance in the other port.
Applying realization #2 of Transimpedance Amplifier in Table 4.5 to the meta-
mutator with AD-IC, connecting Is and Rn to ports l and n respectively then
applying an open circuit to port m of the metamutator, the voltage in port k will
be equal to Is multiplied by the resistance in port n. The circuit of the resulting
transimpedance amplifier is shown in Figure 4.19.
In this case, according to (3.20), the voltage at port k will be equal to Is multiplied
by the resistance in port n as shown with (4.24),
vk 1
vk = −Rn.Is ⇒ | A |=| |= (Ω) (4.24)
Is Rn
91
Figure 4.19: Circuit of transimpedance amplifier realization #2 of Tran-
simpedance Amplifier
Equality (4.24) confirms the operation of the circuit in Figure 4.19 as transimp-
dance amplifier. Moreover, the frequency I/O characteristics are given in Figure
4.20.
Figure 4.20: I/O characteristics vs frequency of transimpedance amplifier
The transimpedance amplifier of Figure 4.19 was simulated using an AC current
source with amplitude of 100µA. As for AD-IC, TSMC, 0.25µm CMOS process
92
parameters were used with transistor dimensions as shown in Table 3.6 and the
circuit in Figure 3.48. The supply voltages were chosen as ±1.25V and VB as
0.8V. The values of Rn and Rk were selected as 5KΩ and 100MΩ respectively. It
can be clearly observed that the circuit operates as a transimpedance amplifier
in a wide frequency range.
4.2.3 Voltage Mode Multiple Input Single Output Universal Filter
Universal filters are popular as they can provide several filter functions with the
same circuit and the literature on them is abundant; in [33-41] several multi input
VM universal filters were introduced in contrast to [42-50] in which several multi
output filters are being treated Different kinds of filters can be realized by proper
selection of input voltage terminals in multi-input filters whereas different kinds
of filters are realized by the selection of the output for multi-output filters. In
this subsection VM-MISO filters will be treated.
However, these circuits suffer from one or more of the following problems:
i. In [36-37, 39-41] the necessity of passive component matching conditions,
ii. In [33-35, 38] lack of orthogonal controllability of the resonance angular fre-
quency (ω0) and quality factor (Q),
iii. In [37, 39-40] use of many passive components.
In this subsection a new application of metamutator as VM-MISO universal filters
is being presented. Different realizations of this type of multifunctional filters
using a metamutator were shown in Table 4.5. This new application will be
illustrated by applying the realization in row #1 of multifunctional filter voltage
mode in Table 4.5 to an AD-IC based metamutator.
The resulting block diagram of the universal filter obtained by applying realization
in row #1 of multifunctional filter voltage mode in Table 4.5 is shown in Figure
4.21.
93
Figure 4.21: Universal filter structure
As the ports description matrices of all types of metamutators are the same, the
proposed realizations of filters in Table 4.5 stand true for all of them. According
to (1.9) the output voltage for VIM type metamutators, when all sources are
present, is:
s2C1C2R1R2R3Vs1 + sC2R2R3Vs2 +R1Vs3
Vout(s) = (4.25)
s2C1C2R1R2R3 + sC2R2R3 +R1
By connecting properly elements according to realization in row #1 of multi-
functional filter voltage mode in Table 4.5 to AD-IC based metamutator the
configuration will become as shown in Figure 4.22.
According to (1.9) and (3.20), v2 = v3 and assume that the output is vout = v2 =
v3 KCL at node A of the circuit in Figure 4.22 gives:
− (vs2 − Vout)I2 = sC1(Vs1 Vout) + (4.26)
R1
94
Figure 4.22: VIM based VM-MISO universal filter
Using i2 = i1 and v1 = −v4 from (3.20), i1 = −v1/R3 = v4/R3 and V4 =
(V3 − Vs3)/sR2C2 in (4.26) gives:
− sC2R2R3V3 Vs3 = s2C1C2R2R3(Vs1 − V out) + (Vs2 − Vout) (4.27)
R1
As v3 = Vout , solving for Vout in terms of source voltages, the output voltage
when all sources are present, is obtained as shown by (4.27) with the selection
of various voltage sources resulting in different filter functions as illustrated by
Table 4.6.
Selection Vs1 Vs2 Vs3 Filter Type
#I Vin 0 0 High-Pass
#II 0 0 Vin Low-Pass
#III 0 Vin 0 Band-Pass
#IV Vin 0 Vin Band-Notch
#V Vin −Vin Vin All-Pass
Table 4.6: Different filter types depending on voltage source locations
All filter functions and their simulated characteristics will be displayed in Table
4.7 and Figure 4.23 respectively.
95
Filter Function Filter Type
1 High-Pass
V s2out C1C2R3R2
(s) =
V 2 C2R3R2in s C1C2R3R2 + s + 1R1
2 Low-Pass
Vout 1
(s) =
V 2 C2R3R2in s C1C2R3R2 + s + 1R1
3 Band-Pass
sC2R3RV 2out
(s) = R1
V 2in s C1C2R3R2 + s
C2R3R2 + 1
R1
4 Notch
V s2out C1C2R3R2 + 1
(s) =
V 2 C2R3R2in s C1C2R3R2 + s + 1R1
5 All-Pass
s2C C R R + sCV 2
R3R2
out 1 2 3 2 + 1
(s) = R1
V 2 C2R3R2in s C1C2R3R2 + s + 1R1
Table 4.7: Transfer functions of different filters
Figure 4.23: Simulation results of all filter types
The filter in Figure 4.22 was simulated by applying an AC voltage source with
amplitude of 1 V to all inputs, one by one, following Table 4.5. For element
values,R1 = R2 = R3=1kΩ and C1 = C2= 25pF were taken. As for AD-IC,
96
TSMC, 0.25µm CMOS process parameters were used with transistor dimensions
as shown in Table 3.6 and the circuit in Figure 3.48. The supply voltages were
chosen as ±1.25V and VB as 0.8V.
There is no requirement for matching conditions in any of the filter realizations.
The angular resonance frequency ω0 and the quality factor Q of all filters are:
1
w0 = √ (4.28)
C1C2R2R3
√
C1
Q = R1 (4.29)
C2R2R3
w0 G1
BW = = (4.30)
Q C1
As shown by (4.28)-(4.30), the angular frequency can be controlled byR2 and/or
R3 and the quality factor can be independently controlled by R1. So the angular
frequency and quality factor are orthogonally controllable. In this case, as C1 =
C2 = C= 25Pf and R1 = R2 = R3 = R= 1kΩ the angular frequency becomes
ω0 = 1/RC = 4.10
7(rad/s) and the quality factor is Q = 1.
Using expressions (4.28)-(4.30) sensitivities become,
W − 1S 0G ,G = S
W0
C ,C = (4.31)1 2 1 2 2
SQ
1
G = −1, S
Q Q
G ,G ,C = −SC = (4.32)1 2 3 1 2 2
SBWG = −SBWC = 1 (4.33)1 1
97
The absolute values of calculated sensitivities are low and equal to unity only for
bandwidth sensitivities.
4.2.4 Current Mode Single Input Multiple Output Universal Filter
CM filters have received significant attention due to their advantages such as
higher frequency of operation, larger dynamic range, simpler circuitry and less
power dissipation compared to their VM counterparts [42-47].
Universal filters are popular as they can provide several filter functions with the
same circuit and the literature on them is abundant. To cite a few: in [47]
a Single-Input Three-Output filter with four active devices (DOCCII) and five
passive components, each DOCCII consisting of 20 MOS transistors, in [42] a
Three-Input Single-Output filter with two active devices (CCCCTA) and two
passive components, each CCCCTA consisting of 54 BJT transistors, in [43] a
Three-Input Single-Output filter with two active devices (CFTA) and two pas-
sive components, each CFTA consisting of 25 MOS transistors, in [44] a Fully
Differential Current Mode Universal Filter with seven active devices (CDCC)
and two passive components, each CDCC consisting of 46 MOS transistors, in
[45] a universal filter with single-input three-output only one active device FD-
CCII and four passive components, FDCCII consisting of 59 MOS transistors,
in [46] a biquadratic filter with one active device (VDCC) and three grounded
passive components, VDCC consisting of 22 MOS transistors, are given. All of
these filters operate in Current Mode. Commercial monolithic IC universal filters
such as LTC1562 [48], UAF42 [49] and MF10 [50] are also available.
In the sequel a new application of metamutator as CM-SIMO universal filter is
being presented. Different realizations of this type of multifunctional filter have
been shown in Table 4.8. This new application of CIM metamutator, will be
investigated by applying the realization in row #4 of Table 4.8.
98
Realization R3 C4||R4||Iin C2 R1
#1 Port n Port l Port k Port m
#2 Port k Port m Port n Port l
#3 Port l Port n Port m Port k
#4 Port m Port k Port l Port n
Table 4.8: Multifunctional filter realizations
By applying realization #4 of Table 4.8 to AD-IC based metamutator, the circuit
diagram of CM-SIMO universal filter will be obtained as shown in Figure 4.24.
Figure 4.24: Circuit diagram of the CM-SIMO universal filter
For investigating the operation principle of CM-SIMO universal filter, the real-
ization #4 is applied to the metamutator with AD-IC, as shown below,
Writing KVL, KCL and using element defining relations and solving for IBP1, IBP2,
IBP3, ILP1, ILP2 and IHP in terms of Iin results in filter functions as shown in Table
4.9.
99
Figure 4.25: Current mode filter realization #4
Filter Type Transfer Function
Band pass
s2R1C2R3C4R4 − sR1C2R3 +R4
IAP (s) = I (s)
s2
in
R1C2R3C4R4 + sR1C2R3 +R4
Band pass
s2R1C2R3C4R4 − sR1C2R3 +R4
IAP (s) = Iin(s)
s2R1C2R3C4R4 + sR1C2R3 +R4
Low pass
s2R1C2R3C4R4 − sR1C2R3 +R4
IAP (s) = I (s)
s2
in
R1C2R3C4R4 + sR1C2R3 +R4
High pass
s2R1C2R3C4R4 − sR1C2R3 +R4
IAP (s) = I (s)
s2
in
R1C2R3C4R4 + sR1C2R3 +R4
Table 4.9: Transfer function of different filters
According to description matrix of metamutator as i1 = i2 and i3 = i4 so are
IBP1 = IBP2 and ILP1 = ILP2. As seen from Table 4.9 the newly introduced
current mode filter enables Low Pass, Band Pass and High Pass responses simul-
taneously. One can obtain the Band Stop filter by adding the ILP and IHP or an
100
All Pass filter by adding up the negative of IBP to the sum of ILP and IHP . In
these cases, the transfer functions become as given by (4.34) and (4.35) and the
frequency behavior of all filters is shown in Figure 4.26.
s2R1C2R3C4R4 +R4
IBS = Iin (4.34)
s2R1C2R3C4R4 + sR1C2R3 +R4
s2R1C2R3C4R4 − sR1C2R3 +R4
IAP = Iin (4.35)
s2R1C2R3C4R4 + sR1C2R3 +R4
Figure 4.26: Simulation results of all type filters
The filter in Figure 4.25 was simulated by applying an AC current source with
amplitude of 10mA to port 4 and selecting resistor and capacitor values as R1 =
R3 = R4=1kΩ and C2 = C4=10nF
following Table 4.8. As for AD-IC, TSMC, 0.25µm CMOS process parameters
were used with transistor dimensions as shown in Table 3.6 and the circuit in
Figure 3.48 The supply voltages were chosen as ±1.25V and VB as 0.8V.
The angular frequency ω0 , quality factor Q and Bandwidth for all types of filters
are obtained as:
w0 = √
1
(4.36)
R1C2R3C4
101
√
C4
Q = R4 (4.37)
R1C2R3
w0 G4
BW = = (4.38)
Q C4
The quality factor (Q) and bandwidth are independent from angular frequency
(ω0) and can be independently adjusted by changing the value of passive compo-
nent R4.
In particular, choosing C2 = C4 = C and R1 = R3 = R4 = R the angular
frequency becomes ω0 = 1/RC and the quality factor Q = 1. In this case all
filters have non-inverting unity gain.
Using expressions (4.36)-(4.38) sensitivities become,
SW0 W
1
0
G1,G
= −S = (4.39)
3 C4,C2 2
SQG = −
1
1, SQ Q
4 G1,G3,C
= −S
4 C
= (4.40)
2 2
SBWG = −SBWC = 1 (4.41)4 4
(ω )
The sensitivities in (4.39)-(4.41) are all single parameter sensitivities e.g. S 0(G =1,G3)
(ω ) (ω )
1/2 means that S 0 = S 0(G ) (G ) = 1/2 . The absolute values of calculated sensitivi-1 3
ties are low and equal to unity only for bandwidth sensitivities.
102
Chapter 5
Two Operationally Nonlinear Applications of AD-IC
5.1 Analog Multiplier
Nonlinear building blocks like multipliers and dividers are widely used in sev-
eral applications in analog signal processing. For example, applications such as
mixers, modulators, adaptive filters. are composed of analog multipliers. In the
literature different techniques have been applied for designing analog multipliers
[51-59]. But, the growing interest in the design of fully integrated systems on
chip encourages the inclusion of active blocks in their structures. Several analog
multipliers using active building blocks are mentioned here.
In [51-52] second-generation Current Conveyors (CCIIs), in [53-54] Current Con-
trolled Conveyors (CCCIIs), in [55] Dual-X Current Conveyors (DXCCIIs), in [56]
current controlled current differencing buffered amplifiers (CCCDBAs), in [57-58]
transconductors, in [59] Operational Transconductance Amplifiers (OTAs) are
used for building analog multipliers.
However most of these analog multipliers suffer from one or more of the following
disadvantages:
i. Excessive numbers of active devices [54], [59],
ii. Additional active or passive resistors [53],
103
iii. Complex internal circuitry of active device [54-56], [58],
iv. Appearance of the process parameters’ dependent components at the output
of the multiplier [55],
v. Excessive number of transistors [56-59].
Most of these realizations are not able to be fabricated as an integrated CMOS
system on chip. For example, the circuits in [51-54], [56], [58-59] use bipolar or
bipolar-JFET technology which involve more expensive processes. The complex-
ity of the CMOS implementations given in [55] and [57] prevents the realization
of the analog multipliers using commercially available CMOS circuits. Thus, it
becomes a necessity to realize simple, compact fully CMOS multipliers.
In this section an AD-IC based voltage multiplier is offered. The operation prin-
ciple of the newly proposed multiplier is based on squaring and subtracting the
output voltages of AD-IC. The schematic block diagram of the proposed multi-
plier is shown with Figure 5.1.
Figure 5.1: Block diagram of proposed multiplier
In the structure of proposed multiplier one AD-IC active element, a PMOS and
an NMOS squarer circuits, consisting of two transistors each, are being used.
According to (3.19),
104
 vx1 = vy1 − vy2 = v1 − v2 (5.1)vx2 = vy1 + vy2 = v1 + v2
For NMOS and PMOS based squarer circuits the structures shown in Figure 5.2
(a) and (b) extracted from [60] are used. Transistor dimensions are given with
Table 5.1.
Figure 5.2: Voltage in/current out squarer circuits: (a) NMOS-based, (b)
PMOS-based
NMOS Transistor W(µm)/L(µm)
M1,M2 3.6/1.8
PMOS Transistor W(µm)/L(µm)
M1,M2 3.6/1.8
Table 5.1: Transistor dimensions of the squarer circuits
When NMOS based squarer circuit is in positive cycle of vin, M1 is off and M2 is
in saturation region; when NMOS based squarer circuit is in negative cycle of vin,
M2 is off and M1 is in saturation region. Thus, the output current of the squarer
for the whole cycle of input voltage is:
1
I 2outN = KnVin (5.2)
2
105
Here Kn1 = Kn2 = Kn with K
W
n = µnCox and W/L is the transistor aspectL
ratio, µn is electron mobility, and Cox is the gate oxide capacitance per unit area
and the threshold voltages VTN of NMOS transistors are assumed to be equal.
When PMOS based squarer circuit is in positive cycle of vin, M2 is off and M1 is
in saturation region; when PMOS based squarer circuit is in negative cycle of vin,
M1 is off and M2 is in saturation region. Thus the output current of the squarer
for the whole cycle of input voltage is:
1
I 2outP = KpVin (5.3)
2
Here Kp1 = Kp2 = Kp with Kp = µpC
W
ox and W/L is the transistor aspect ratio,L
µp is electron mobility, and Cox is the gate oxide capacitance per unit area and
the threshold voltages VTP of PMOS transistors are assumed to be equal. So the
currents i1, i2 and Iout in Figure 5.1 can be calculated as,
 I Kn 2outN = i2 = (v2 1 − v2) (5.4)I = i = Kp (v + v )2outP 1 2 1 2
Kp Kn
I 2 2out = i1 − i2 = [ (v1 + v2) − (v1 − v2) ] (5.5)
2 2
By selecting, Kp = Kn = K, the output current Iout can be expressed as,
Iout = 2Kv1v2 (5.6)
By terminating the output of the multiplier with a resistor RL, when a voltage
mode operation is desired, the output voltage can be expressed as:
vout = KMv1v2 (5.7)
106
where 2RLK = KM . As it can be seen from (5.6) and (5.7) the proposed multiplier
can operate in both transconductance- and in voltage-mode.
The most significant application of multipliers being to operate as modulator, in
the remainder of this section, AD-IC based multiplier circuit’s Amplitude Modu-
lation (AM) capability will be illustrated.
By applying two sinusoidal voltage sources with different frequencies, one as mes-
sage signal and the other one as carrier signal, to the inputs of multiplier circuit,
it will operate as a modulator. The simulation results are shown in Figure 5.3.
Figure 5.3: Simulation result of multiplier as modulator
The modulator circuit is simulated by applying two sinusoidal voltage sources,
one as message signal with amplitude of 100mV and frequency of 100Hz and the
other one as carrier signal with amplitude of 200mV and frequency of 2000Hz.
As for PMOS and NMOS squarer circuits transistors with process parameters
TSMC, 0.18µm CMOS were used with dimensions as shown in Table 5.1 and the
circuit structures proposed in Figure 5.2; supply voltages were chosen as ±0.4V.
For AD-IC, TSMC, 0.25µm CMOS process parameters were used with transistor
dimensions as shown in Table 3.6 and the circuit in Figure 3.48, the supply
voltages were chosen as ±1.25V and VB as 0.8V. vout in Figure 5.3 confirms the
operation of the AD-IC based multiplier as modulator.
107
5.2 Full-Wave Rectifier
Precision rectifiers are widely used in many fields such as analog signal processing,
control engineering, communications and also in measurement applications and
instrumentation such as AC voltmeters and ammeters, averaging circuits, signal-
polarity detectors, peak-value detector rectifications [61-62].
In general rectifier circuits, consisting of diodes and several passive components
exist in the literature but because of the threshold voltage limitations of diodes,
which are about 0.3V and 0.7V for germanium and silicon diodes respectively, the
usage of these types of rectifiers for high-precision and low-voltage applications
are not suitable. Consequently, for high-precision rectification and/or achieving
wider frequency response ranges, active elements have been used. Many different
topologies of rectifiers, with one or more active IC devices in their structures,
have been introduced in [63-81]. However, these circuits suffer from one or more
of the following disadvantages:
i. quite a large number of transistors,
ii. high area occupancy,
iii. high power consumption [69-78],
iv. and necessity of satisfying different element matching conditions [63-69].
By connecting terminal y1 of AD-IC to ground, applying a voltage source as
input to terminal y2 and connecting diodes D1 and D2 to terminals x1 and x2
respectively the structure of the proposed voltage mode full-wave rectifier will
become as shown in Figure 5.4. The most important feature of the proposed
circuit is its simple structure containing only twelve NMOS transistors and two
diodes.
To see that the configuration in Figure 5.4 operates indeed as a full wave rectifier
consider the following:
108
Figure 5.4: Block diagram of AD-IC
• As one can observe the terminal y1 is grounded hence vy1 = 0 and in this
case, vx1 which is equal to vy1 − vy2 will be equal to −vin.
• on the other hand vx2 which is equal to vy1 + vy2 will be equal to vin.
When the input of the proposed full-wave rectifier has positive values, denoted
by vin(t)+, the voltage at terminal x1 is equal to −vin and the voltage at terminal
x2 is equal to vin, so D1 is off and D2 is on yielding:
vout(t) = vin(t)+ (5.8)
When the input of the proposed full-wave rectifier has negative values, denoted
by vin(t)−, the voltage at terminal x1 is equal to vin and the voltage at terminal
x2 is equal to −vin , so D1 is on and D2 is off giving:
vout(t) = −vin(t)− (5.9)
The input voltage of the proposed full-wave rectifier can be expressed as,
vin(t) = vin(t)+ + vin(t)− (5.10)
109
From (5.8), (5.9) and (5.10) it can be concluded that the output voltage of pro-
posed full-wave rectifier can be given as,
vout(t) =| vin(t) | (5.11)
which proves that the circuit proposed in Figure 5.4 operates as a full-wave rec-
tifier. The proposed AD-IC based rectifier circuit has the following advantages:
i. Voltage-mode operation,
ii. Low-output, high-input impedances which make it suitable for IC fabrication
without the need of any additional buffer circuits,
iii. Fewer CMOS transistors with respect to rectifiers in [64-78],
iv. No resistors are used hence there is no need of resistive matching conditions.
By applying a sinusoidal voltage source with amplitude of 100 mV and frequency
of 1kHz to the input of the circuit in Figure 5.4, the time domain waveforms of vin
and vout and, the DC transfer characteristic of the full-wave rectifier are shown in
Figure 5.5 and Figure 5.6 respectively. For diodes D1 and D2 the 1N4148 model
is used. The supply voltages are chosen as ±1.25V and VB as 0.8V.
From both, Figure 5.5 and Figure 5.6 it can be seen that the output waveform
and the DC characteristic of the proposed rectifier are in very good agreement
with the expected behavior.
Another set of parameters to evaluate the behavior of the proposed full-wave
rectifier and enable its comparison with other full-wave rectifier circuits are the
DC value transfer (PDC) and RMS error (PRMS). These values are defined with
(5.12) and (5.13) respectively where voa(t) and voi(t) represent the actual and
ideal output signals of rectifier and T is the period of the rectified signal. (5.12)
110
Figure 5.5: Time-domain input and output waveforms of the rectifier with
AD-IC
Figure 5.6: DC characteristics of the non-inverting full-wave rectifier circuit
and (5.13) imply that the ideal values for PDC and PRMS are unity and zero
respectively.
∫
PDC = ∫ voatdtT (5.12)
v
T oi
tdt
√∫
[voa(∫t)− voi(t)]2dtP TRMS = (5.13)
Tv2oi(t)dt
The characteristics in Figure 5.7 clearly show that as the input frequency in-
creases, the value of PDC decreases and that of PRMS increases due to the non-
ideal effects present in the rectifier. In order to show how well the newly proposed
111
Figure 5.7: PDC ,P(RMS) characteristics of the rectifier in 100mV input ampli-
tude
rectifier circuit with AD-IC behaves, a comparison with previously published rec-
tifiers has been presented in Table 5.2.
paper #of ICs #of #of Re- High In / Res.
Transis- sistors Low Out Match
tors Impedance Re-
quired
[64] 2 OTA >> 12 7 NO/YES YES
[66] 2 CCII >> 12 2 YES/NO YES
[68] 1 CCII- 15 2 NO/NO YES
[69] 1CCII,1 DXCCII 29 2 YES/NO YES
[70] 2 CCII 36 2 YES/NO YES
[71] 1 DO-OTA 24 1 YES/NO NO
[72] 1 CCII,1 OpAmp 41 3 YES/YES YES
[73] 2 CCII 80 3 YES/NO YES
[74] 2 CCII 36 2 YES/YES YES
[75] 2 CCII 42 2 YES/NO NO
[76] 2 CCII,1 Buffer 26 4 YES/NO YES
[77] 2 DVCC 24 26 YES/YES YES
[78] 4 CCCII 60 5 YES/NO YES
[79] 2CFOA, 3/2NMOS 39/38 0/1 YES/YES YES
Here 1AD-IC 12 2 YES/YES NO
Table 5.2: Comparison of the proposed rectifier with others
112
Chapter 6
Conclusion
A brief introduction to basic circuit elements together with a new class of memory
elements namely, memstors were presented in the first chapter. Also, the necessity
of using mutators together with previously developed mutator circuits in literature
was considered. A brief overview of 4-port metamutators according to their port
description matrices, their classification into two categories: Voltage Inverting
Metamutator (VIM) and Current Inverting Metamutator (CIM) were presented.
The necessity of using mutators and the basic definition of 2-port mutators with
their port relation matrices and different kind of mutators for mutating nonlinear
circuit elements to memristors or converting memristors to other non-volatile
circuit elements like meminductor and memcapacitor, also some of the previously
developed classical mutator circuits well-known in the literature, were presented
in the second chapter.
Many incognito mutator-like 4-ports hidden in the simulations/emulations of de-
vices in the literature have been uncovered and named metamutator in the third
chapter. In addition to introducing some of these incognito metamutator realiza-
tions, newly designed metamutator circuits with one or two active devices, with
their ports relation matrices and their different realization tables were presented.
Also a novel realization of a metamutator with single active device, Additive and
Differential IC (AD-IC) was proposed and implemented with twelve transistors
only; a minimal number among all realizations.
113
In the fourth chapter, different applications of metamutators developed during
the research period of this thesis were presented. As the port description matrix
of all introduced metamutators in Chapter 3 are the same, these applications
stand true for all of metamutator realizations. Depending on how some of the
ports are terminated, many metamutator applications, which can be classified
into two groups, is attained:
I. 1-port circuits realized with metamutators,
II. 2-port circuits realized with metamutators.
It has been shown in this chapter that in 1-port realizations, by properly termi-
nating three ports of the metamutator the resulting circuit behaves like a mu-
tator, floating and/or grounded impedance scalor, oscillator. In addition, fourth
chapter also contains new 2-port realizations: transconductance/transimpedance-
amplifiers, voltage mode multiple input single output universal filters and current
mode single input multiple output universal filters. Also, a list of all of these ap-
plications were demonstrated with Table 1.3 and Table 4.5. The advantages of
the introduced circuits were demonstrated and these applications were verified
in detail with PSPICE simulations using transistor parameters obtained from
layout level descriptions of metamutators. Comparisons between simulation and
theoretical results were also presented.
In the fifth chapter, two new applications: a voltage multiplier with single AD-IC
and two squarer circuits consisting of two transistors each, and a full-wave recti-
fier again with only an AD-IC and two diodes in its configuration were presented.
Both of the circuits were simulated with parameters extracted from the layout
and have shown very good conformity with ideal voltage multiplier and full-wave
rectifier behaviors. Also detailed comparison tables of the proposed analog mul-
tiplier and full-wave rectifier with others existing in the literature, were included
in this chapter.
114
Future work will concentrate on the comparison of VIM versus CIM, novel types
of metamutators, their different realizations, tuning with external elements to
improve the behavior of these circuits and further applications. Comparing the
effects of using different kind of metamutators in the design of filters realized here
will deserve special consideration.
115
References
[1] Chua, L.O.,“Memristor–the missing circuit element,” IEEE Trans. on Cir-
cuit Theory, vol. 18, PP. 507– 519, 1971.
[2] Chua, L.O. and Kang, S.,“Memristive Devices and Systems,” IEEE Trans.
on Circuit Theory, vol. 64, no. 2, pp. 209- 222, 1976.
[3] Pershin, Y.V. and Di Ventra, M., “Experimental demonstration of associative
memory with memristive neural networks,” Neural Networks, vol. 23, no. 7,
PP. 881– 886, 2010.
[4] Minaei, S., Goknar, I. C., Yildiz, M. and Yuce, E., “Memstor, Memstance
Simulations via a Versatile 4-port Built with New Adder and Subtractor
Circuits,” International Journal of Electronics, vol. 102, PP. 911– 931, 2013.
[5] Chua, L.O., “Synthesis of New Nonlinear Network Elements,” Proceedings
of the IEEE, vol. 56, no. 8, PP. 1325-1340, 1968.
[6] Goknar, I.C., Oncul, F. and Minayi, E., “New Memristor Applications: AM,
ASK, FSK, and BPSK Modulators,” IEEE Antennas and Propagation Mag-
azine, vol. 55, pp. 304-313, 2013.
[7] Pershin, Y.V. and Di Ventra, M., “Memristive Circuits Simulate Memcapac-
itors and Meminductors,” Electronics Letters, vol. 46, no. 7, pp. 517-518,
2010.
[8] Biolek, D. and Biolkova, V., “Mutator for Transforming Memristor into
Memcapacitor,” Electronics Letters, Vol. 46, no. 21, pp. 1428-1429, 2010.
116
[9] Biolek, D., Biolkova, V. and Kolka, Z., “Mutators Simulating Memcapacitors
and Meminductors,” IEEE Asia Pacific Conference on, Circuits and Systems
(APCCAS), pp. 800-803, December 6-9, 2010.
[10] Biolek, D., Bajer, J., Biolkova, V. and Kolka, Z., “Mutators for Transforming
Nonlinear Resistor into Memristor,” 20th European Conference on Circuit
Theory and Design (ECCTD), pp. 488-491, August 29-31, 2011.
[11] Pershin, Y. V. and Ventra, M. Di, ”Emulation of floating memcapacitors and
meminductors using current conveyors,” Electronics Letters, Vol. 47, no. 4,
pp. 243-244, 2011.
[12] Minayi, E., and Goknar, I. C., ”CIM a current inverting metamutator and
its application to universal filters among others,” 40th International Con-
ference on Telecommunications and Signal Processing (TSP), pp. 289-293,
Barcelona, 2017.
[13] Minayi, E., and Goknar, I. C., ”Single active device metamutator; Its appli-
cation to impedance simulation and in particular to FDNR,” 10th Interna-
tional Conference on Electrical and Electronics Engineering (ELECO), pp.
499-502, Bursa, Turkey, 2017.
[14] Minayi, E., and Goknar, I. C., ”Current inverting metamutator, its imple-
mentation with a new single active device and applications,” Analog Inte-
grated Circuits and Signal Processing, vol. 97, pp. 15–25, 2018.
[15] Sanchez-Lopez, C., Mendoza-Lopez, J., Carrasco-Aguilar, M. and Muñiz-
Montero, C., “A Floating Analog Memristor Emulator Circuit,” IEEE
Transactions on Circuits and Systems II: Express Briefs, vol. 61, pp. 309-313,
2014.
[16] Liang, Y., Chen, H., and Yu, D. S., “A Practical Implementation of a Float-
ing Memristor-Less Meminductor Emulator,” IEEE Transactions on Circuits
and Systems II: Express Briefs vol. 61, no. 5, pp. 299-303, May 2014.
117
[17] Yu, D., Liang, Y., Iu, H. H. C., Chua, L. O., “A universal mutator for
transformations among memristor, memcapacitor, and meminductor,” IEEE
Trans. Circuits and Systems II, vol. 61, pp. 758-762, 2014.
[18] Alharbi, A. G., Khalifa, Z. J., Fouda, M. E. and Chowdhury, M. H., ”Mem-
ristor emulator based on single CCII,” 27th International Conference on Mi-
croelectronics (ICM), vol. 18, PP. 507– 519, 1971. pp. 174-177, Casablanca,
2015.
[19] Kumngern, M., “A floating memristor emulator circuit using operational
transconductance amplifiers,” IEEE International Conference on Electron
Devices and Solid-State Circuits (EDSSC), pp. 679-682, Singapore, 2015.
[20] Alharbi, A. G., Fouda, M. E., Khalifa, Z. J. and Chowdhury, M. H ”Simple
generic memristor emulator for voltage-controlled models,” IEEE 59th In-
ternational Midwest Symposium on Circuits and Systems (MWSCAS), pp.
1-4, Abu Dhabi, 2016.
[21] Stork, M., ”Properties of one type memristor emulator,”28th International
Conference Radioelektronika (RADIO ELEKTRONIKA), pp. 1-6, Prague,
2018.
[22] Sedra, A. S. and Smith, K. C., “A Second-Generation Current Conveyor and
Its Applications,” IEEE Trans. Circuit Theory, vol. 17, no. 1, pp. 132–134,
1970.
[23] Yildiz, M., Minaei, S., Ozoguz, S., ”Linearly weighted Classifier Circuit,”
Joint IEEE North-East Workshop on Circuits and Systems and TAISA Con-
ference NEWCAS-TAISA pp. 1-4, 28 June -1 July 2009.
[24] Minayi, E., “Applications of 4-port generalized mutators to memstor simu-
lations,” M. Sc. Thesis, Dogus University, 2014.
[25] Minayi, E., and Goknar, I. C., “Realization of a 4-port generalized mutator
and its application to memstor 1 simulations,” 8th International Conference
118
on Electrical and Electronics Engineering (ELECO) pp. 5-8, Bursa, Turkey,
28-30 November 2013.
[26] Goknar, I. C., and Minayi, E., ”Realizations of mutative 4-ports and their
applications to memstor simulations,” Analog Integrated Circuits and Signal
Processing vol. 81, pp. 29–42, 2014.
[27] Yuce, E. and Minaei, S., “On the Realization of Simulated Inductors with
Reduced Parasitic Impedance Effects”, Circuits, Syst. Signal Process vol. 28,
no.3, pp. 451-465, 2009.
[28] Joglekar, Y. N. and Wolf, S. J., “The Elusive Memristor: Properties of Basic
Electrical Circuits”, Eur. J. Phys., vol. 30, pp. 661-675, 2009.
[29] Ibrahim, M. A, Minaei, S., Yuce, E., Herencsar, N. and Koton, J.,
“Lossy/lossless floating/grounded inductance simulation using one DDCC”,
Radio Engineering vol. 21, pp. 3-10, 2012.
[30] Kacar, F., “New lossless inductance simulators realization using minimum
active and passive components”, Microelectronics Journal vol. 41, pp. 109-
113, 2010.
[31] Chen, H. P. and Yang, W. S., “High-input and low-output impedance
voltage-mode universal DDCC and FDCCII filter”, IEICE Transactions on
Electronics vol. 91-C, pp. 666-669, 2008.
[32] Bruton, L.T., RC-Active Circuits: Theory and Design, Englewood Cliffs,
NJ: Prentice-Hall, 1980.
[33] Chen, H. P. and Yang, W. S., “High-input and low-output impedance
voltage-mode universal DDCC and FDCCII filter”, IEICE Transactions on
Electronics vol. 91-C, pp. 666-669, 2008.
[34] Horng, J.W., “High input impedance voltage-mode universal biquadratic fil-
ter with three inputs using DDCCs,”Circuits, Systems, and Signal Processing
vol. 27, pp. 553-562, 2008.
119
[35] Chen, H.P., “Versatile multifunction universal voltage-mode biquadratic fil-
ter,” AEU International Journal of Electronics and Communications vol. 64,
pp. 983-987, 2010.
[36] Minaei, S., and Yuce, E., “All-grounded passive elements voltage-mode
DVCC-based universal filters”, Circuits, Systems, and Signal Processing vol.
29, pp. 295-309, 2010.
[37] Nikoloudis, S. and Psychalinos, C., “Multiple input single output universal
biquad filter with current feedback operational amplifiers,” Circuits Systems,
and Signal Processing vol. 29, pp. 1167-1180, 2010.
[38] Lee, C. N., “Fully cascadable mixed-mode universal filter biquad using DD-
CCs and grounded passive components,” Journal of Circuits, Systems, and
Computers vol. 20, pp. 607-620, 2011.
[39] Topaloglu, S. and Sagbas, M. and Anday, F., “Three-input single-output
second-order filters using current-feedback amplifiers,” AEU International
Journal of Electronics and Communications vol. 66, pp. 683-686, 2012.
[40] Horng, J. W., Hsu, C. H., and Tseng, C. Y., “High input impedance voltage-
mode universal biquadratic filters with three inputs using three CCs and
grounding capacitors,” Radioengineering vol. 21, pp. 290-296, 2012.
[41] Horng, J. W., Chiu, T. Y., and Jhao, Z. Y., “Tunable versatile high in-
put impedance voltage-mode universal biquadratic filter based on DDCCs,”
Radioengineering vol. 21, pp. 1260-1268, 2012.
[42] Kanchana, S, Noppakarn, Sakul, A. C. and Jaikla, W., ”Current controlled
current-mode universal filter using CCCCTAs,” International Conference on
Electrical Machines and Systems pp. 1-4., Beijing, 2011.
[43] Tomar, R.S., Singh, S.V. and Chauhan, C., ”Fully integrated electronically
tunable universal biquad filter operating in current-mode,” International
Conference on Signal Processing and Integrated Networks (SPIN) , pp. 549-
554, Noida, 2014.
120
[44] Singh, A.K. and Kumar, P., ”A novel fully differential current mode univer-
sal filter,”IEEE International Midwest Symposium on Circuits and Systems
(MWSCAS) pp. 579-582, College Station, TX, 2014.
[45] Nonthaputha, T. and Kumngern, M., ”Current-mode universal filter using
FDCCII,” International Conference on ICT and Knowledge Engineering pp.
32-35, Bangkok, 2014.
[46] Lamun, P. P. and Torteanchai, U., ”Single VDCC-based current-mode uni-
versal biquadratic filter,” International Conference on Information Technol-
ogy and Electrical Engineering (ICITEE) pp. 122-125, Chiang Mai,2015.
[47] Minaei, S., Kuntman, H., Cicekoglu, O., Turkoz, S. and Tarim, N., ”A new
high output impedance current-mode universal filter with single input and
three outputs using dual output CCIIs,” IEEE International Conference on
Electronics, Circuits and Systems pp. 379-382, vol.1, Jounieh, 2000.
[48] http://www.linear.com/product/LTC1562.
[49] http://www.ti.com/product/uaf42.
[50] http://www.maximintegrated.com/en/products/analog/analog-
filters/MF10.html
[51] Narksarp, W., Pawarangkoon, P., Buakaew, S., Kiranon, W., and Wardkein,
P., “A Four Quadrant Multiplier Based on CCII+s,” Proc. of Int. Conf.
on Electrical Engineering, Electronics, Computer, Telecommunications and
Information Technology (ECTI-CON) pp. 225-228, Chiang Mai, Thailand,
19-21 May 2010.
[52] Liu, S. I., Wu, D. S., Tsao, H. W., Wu, J. And Tsay, J. H., “Nonlinear
Circuit Applications with Current Conveyors,” IEE Proceedings-G vol. 140,
no. 1, pp. 1-6, 1993.
[53] Yuce, E., “Design of a Simple Current-Mode Multiplier Topology Using a
Single CCCII+”,IEEE Trans. Inst. Measur vol. 57, pp. 631-636, 2008.
121
[54] Petchakit, W., Kiranon, W., Wardkien, P. and Petchakit, S., “A Current-
Mode CCCII-Based Analog Multiplier/Divider,”Proc. of Int. Conf. on Elec-
trical Engineering, Electronics, Computer, Telecommunications and Infor-
mation Technology (ECTI-CON) pp. 221-224, Chiang Mai, Thailand, 19-21
May 2010.
[55] Zeki, A., Keskin, A. U. and Toker, A., “DXCCII-based Four- Quadrant
Analog Multipliers Using Triode MOSFETs,” Proc. Of 4th Int. Conf. Elec.
Electron. Eng. (ELECO 05) pp. 41-45, Bursa, Turkey, 7-11 December 2005.
[56] Siripruchyanan, M., “A Design of Analog Multiplier and Divider Using
Current Controlled Current Differencing Buffered Amplifiers,” Proc. of Int.
Symposium on Integrated Circuits (ISIC 07) pp. 568-571, Singapore, 26-28
September 2007.
[57] Dei, M., Nizza, N., Lazzerini, G. M., Bruschi, P. and Piotto, M., “A
Four Quadrant Analog Multiplier Based on a Novel CMOS Linear Current
Divider,” Proc. of 5th Conf. on Ph. D. Res. Microelectronics Electronics
(PRIME 09) pp. 128-131, Cork, Ireland, 12-17 July, 2009.
[58] Pisutthipong, N., and Siripruchyanan, M., “A Novel Simple Current-Mode
Multiplier/Divider Employing Only Single Multiple-Output Current Con-
trolled CTTA”,Proc. of IEEE Region 10 Conf. (TENCON 09) pp. 221- 224,
Singapore, 23-26 January, 2009.
[59] Kaewdang, K., Fongsamut, C., and Surakampontorn, W., “A Wide-Band
Current-Mode OTA-Based Analog Multiplier- Divider,” Proc. of Int. Sym-
posium on Circuits and Systems (ISCAS 03) vol. 1, pp. 349-352, Bangkok,
Thailand, 25-28 May 2003.
[60] Minaei, S. and Yuce, E., “New squarer circuits and a current-mode full-wave
rectifier topology suitable for integration”, Radioengineering 19, pp. 657–661,
2010.
122
[61] Sedra, A. S., and Smith, K. C., Microelectronic circuits, (6th ed.,), pp.
1086–1087, Oxford University Press 2011.
[62] Monpapassorn, A., Dejhan, K., and Cheevasuvit, F., “A fullwave rectifier
using a current conveyor and current mirrors,” International Journal of Elec-
tronics vol.88, no.7, pp. 751–758, 2001.
[63] Gift, S.J.G., “A high-performance full-wave rectifier circuit,” Int. Journal of
Electronics vol. 87, no. 8, pp. 925-930, 2000.
[64] Lidgey, F.J., Haytleh, K. and Toumazou, C., “New current-mode precision
rectifiers,” Proc. IEEE Int. Symp. Circuits and Systems pp. 1322-1325, 1993.
[65] Gift, S.J.G., and Maundy, B., “Versatile precision full-wave rectifiers for
instrumentation and measurements,” IEEE Trans Instrum. Meas. vol. 56,
no.5, pp. 1703-1710, 2007.
[66] Biolek, D., Biolkova, V. and Kolka, Z., “AC analysis of operational rectifiers
via conventional circuit simulators,” WSEAS Transactions on Circuits and
Systems vol. 3, no. 10, pp. 2291- 2295, 2004.
[67] Monpapassorn, A., “Low output impedance dual CCII full-wave rectifier,”
Int. J. Electron. vol. 100, no. 5, pp. 648-654, 2013.
[68] Yildiz, M., Minaei, S., Yuce, E., “A High Performance Full-Wave Rectifier
Using a Single CCII-, Two Diodes and Two Resistors,” Scientia Iranica vol.
24, pp. 3280-3286, 2017.
[69] Koton, J., Vrba, K. and Herencsar, N., ”Fast voltage-mode full-wave rectifier
using CCII and DXCCII,” 8th International Conference on Electrical and
Electronics Engineering (ELECO) pp. 49-52, Bursa, Turkey, 2013.
[70] Toumazou, C., Lidgey, F. J., and Chattong, S., “High Frequency Current
Conveyor Precision Full-Wave Rectifier,” Electronics Letters vol. 30, no. 10,
pp. 745–746, 1994.
123
[71] Kumngern, M., “High frequency and high precision CMOS Full-wave rec-
tifier,” IEEE International Conference on Communication Systems (ICCS)
pp. 5–8, 2010.
[72] Gift, S. J. G., and Maundy, B., “Versatile precision full-wave rectifiers for
instrumentation and measurements,” IEEE Transactions on Instrumentation
and Measurements Vol. 56, no. 5, pp. 1703–1710, 2007.
[73] Koton, J., Herencsar, N., and Vrba, K., “Current and voltage conveyors
in current and voltage-mode precision full-wave rectifiers,” Radioengineering
vol. 20, no. 1, pp. 19–24, 2011.
[74] Monpapassorn, A., “Low output impedance dual CCII fullwave Rectifier,”
International Journal of Electronics vol. 100, no. 5, pp. 648–654, 2013.
[75] Stiurca, D., “Truly temperature independent current conveyor precision rec-
tifier”Electronics Letters vol. 31, no. 16, pp. 1302–1303, 1995.
[76] Beg, P. I., Khan, A., and Maheshwari, S., “Biphase amplifier based preci-
sion rectifiers using current conveyors,” International Journal of Computer
Applications vol. 42, no. 3, pp. 14–18, 2012.
[77] Ibrahim, M. A., Yuce, E., and Minaei, S., “A new DVCC based fully cascad-
able voltage-mode full-wave rectifier,” Journal of Computational Electronics
vol. 15, no. 4, pp. 1440–1449, 2016.
[78] Anuntahirunrat, K., Tangsrirat, W., Riewruja, V., and Surakampontorn, W.,
“Sinusoidal frequency doubler and full-wave rectifier based on translinear
current-controlled current conveyors,” International Journal of Electronics
vol. 91, no. 4, pp. 227–239, 2004.
[79] Yuce, E., Minaei, S., Ibrahim, M., “A novel full-wave rectifier/sinusoidal
frequency doubler topology based on CFOAs,” Analog Integrated Circuits
and Signal Processing vol. 93, pp. 351-362, 2017.
124
[80] Minaei, S., Yuce, E., “A new full-wave rectifier circuit employing single dual-
X current conveyor,” Int. J. Electron vol. 95, no. 8, pp. 777–784, 2008.
[81] Kumngern, M, “New versatile precision rectifier,” IET Circuits Devices Syst.
pp. 141–151, 2014.
[82] Ferri, G., Guerrini, N., Silverii, E. and Tatone, A., ”Vibration Damping
Using CCII-Based Inductance Simulators,” IEEE Transactions on Instru-
mentation and Measurement vol. 57, no. 5, pp. 907-914, 2008.
[83] Strukov, D. B, Snider, D G. Stewart, S. R. and Williams, R. S, “The missing
memristor found,” Nature vol. 453, no. 7191, pp. 80–83, 2008.
[84] Mazumder, P., Kang, S. M. and Waser, R., “Memristors: Devices, Models,
and Applications,” Proc. IEEE vol. 100, no. 6, pp. 1911–1919, 2012.
[85] Pershin, Y. V., and Ventra, M. Di, “Practical Approach to Programmable
Analog Circuits with Memristors,” IEEE Trans. Circuits Syst. I Regul. Pap.
vol. 57, no. 8, pp. 1857–1864, 2010.
[86] Hu, M., Chen, Y. J., Yang, J. Y. Wang, and Li, H. H., “A Compact
Memristor-Based Dynamic Synapse for Spiking Neural Networks,” IEEE
Trans. Comput. Des. Integr. Circuits Syst. vol. 36, no. 8, pp. 1353–1366,
2017.
[87] Chen, Q., Wang, X., Wan, H., and Yang, R., “A Logic Circuit Design for
Perfecting Memristor-Based Material Implication,” IEEE Trans. Comput.
Des. Integr. Circuits Syst. vol. 36, no. 2, pp. 279–284, 2017.
[88] Benderli, S. and Wey, T. A., “On SPICE macromodelling of TiO2 memris-
tors,” Electron. Lett. vol. 45, no. 7, p. 377, 2009.
[89] Shin, S., Kim, K. and Kang, S.-M., “Compact Models for Memristors Based
on Charge-Flux Constitutive Relationships,” IEEE Trans. Comput. Des. In-
tegr. Circuits Syst. vol. 29, no. 4, pp. 590–598, 2010.
125
[90] Rak, A. and Cserey, G., “Macromodeling of the Memristor in SPICE,” IEEE
Trans. Comput. Des. Integr. Circuits Syst. vol. 29, no. 4, pp. 632–636, 2010.
[91] Batas, D. and Fiedler, H., “A Memristor SPICE Implementation and a New
Approach for Magnetic Flux-Controlled Memristor Modeling,” IEEE Trans.
Nanotechnol. vol. 10, no. 2, pp. 250–255, 2011.
[92] Abdalla, H., and Abdalla, M. D., “SPICE modeling of memristors,” in
2011 IEEE International Symposium of Circuits and Systems (ISCAS), pp.
1832–1835, 2011.
[93] Biolek, Z., Biolek, D. and Biolková, V., “SPICE Model of Memristor with
Nonlinear Dopant Drift,” Radioengineering vol. 18, no. 2, pp. 210–214, 2009.
[94] Berdan, R., Lim, C., Khiat, A., Papavassiliou, C. and Prodromakis, T., “A
Memristor SPICE Model Accounting for Volatile Characteristics of Practical
ReRAM,” IEEE Electron Device Lett. vol. 35, no. 1, pp. 135–137, 2014.
[95] Patterson, G. A., Sune, J., and Miranda, E., “Voltage-Driven Hystere-
sis Model for Resistive Switching: SPICE Modeling and Circuit Applica-
tions,” IEEE Trans. Comput. Des. Integr. Circuits Syst. vol. 36, no. 12, pp.
2044–2051, 2017.
[96] Yakopcic, C., Taha, T. M., Subramanyam, G., and Pino, R. E., “Gener-
alized Memristive Device SPICE Model and its Application in Circuit De-
sign,” IEEE Trans. Comput. Des. Integr. Circuits Syst. vol. 32, no. 8, pp.
1201–1214, 2013.
[97] Wang, X., Xu, B. and Chen, L., “Efficient Memristor Model Implementation
for Simulation and Application,”IEEE Trans. Comput. Des. Integr. Circuits
Syst. vol. 36, no. 7, pp. 1226–1230, 2017.
[98] Kim, H., Sah, M. P., Yang, Cho, C. S. and Chua, L. O., “Memristor emulator
for memristor circuit applications,” IEEE Trans. Circuits Syst. I Regul. Pap.
vol. 59, no. 10, pp. 2422–2431, 2012.
126
[99] Yesil, A., Babacan, Y. and Kacar, F., “A new DDCC based memristor em-
ulator circuit and its applications,” Microelectronics J. vol. 45, no. 3, pp.
282–287, 2014.
[100] Sanchez-Lopez, C., Mendoza-Lopez J., Carrasco-Aguilar, M. A., and
Muniz-Montero, C., “A floating analog memristor emulator circuit,” IEEE
Trans. Circuits Syst. II Express Briefs vol. 61, no. 5, pp. 309–313, 2014.
[101] Yu, D., Yu, H., Fitch, H. C. A. L. and Liang, Y., “A floating Memristor
emulator based relaxation oscillator,” IEEE Trans. Circuits Syst. I Regul.
Pap. vol. 61, no. 10, pp. 2888–2896, 2014.
[102] Sozen, H. and Cam, U., “Electronically tunable memristor emulator cir-
cuit,” Analog Integr. Circuits Signal Process vol. 89, no. 3, pp. 655–663,
2016.
[103] Babacan, Y. Kaçar, F. and Gurkan, K., “A spiking and bursting neuron
circuit based on memristor,” Neurocomputing vol. 203, pp. 86–91, 2016.
[104] Sanchez-Lopez, C., Carrasco-Aguilar, M. A., and Muniz-Montero, C., “A
16 Hz-160 kHz memristor emulator circuit,” AEU Int. J. Electron. Commun.
vol. 69, no. 9, pp. 1208–1219, 2015.
[105] Sanchez-Lopez, C. and Aguila-Cuapio, L. E., “A 860kHz grounded mem-
ristor emulator circuit,” AEU Int. J. Electron. Commun. vol. 73, pp. 23–33,
2017.
[106] Babacan, Y., Yesil, A. and Kacar, F., “Memristor emulator with tunable
characteristic and its experimental results,” AEU Int. J. Electron. Commun.
vol. 81, pp. 99–104, 2017.
[107] Elwakil, A. S, Fouda, M. E. and Radwan, A. G., “A Simple Model of
Double-Loop Hysteresis Behavior in Memristive Elements,” IEEE Trans.
Circuits Syst. II Express Briefs vol. 60, no. 8, pp. 487–491, 2013.
127
[108] Ayten, U. E., Minaei, S., and Sağbaş, M., “Memristor emulator circuits
using single CBTA,” AEU Int. J. Electron. Commun. vol. 82, pp. 109–118,
2017.
[109] Yener, S. and Kuntman, H., “Fully CMOS memristor based chaotic circuit,”
Radioengineering vol. 23, no. 4, pp. 1140–1149, 2014.
[110] Abuelma’Atti, M. T. and Khalifa, Z. J, “A new memristor emulator and its
application in digital modulation,” Analog Integr. Circuits Signal Process.
vol. 80, no. 3, pp. 577–584, 2014.
[111] Abuelma’atti, M. T. and Khalifa, Z. J., “A continuous-level memristor em-
ulator and its application in a multivibrator circuit,” AEU Int. J. Electron.
Commun. vol. 69, no. 4, pp. 771–775, 2015.
[112] Raj, R. K. N., Bhuwal, N. and Khateb, F., “Single DVCCTA based high
frequency incremental/decremental memristor emulator and its application,”
AEU Int. J. Electron. Commun. vol. 82, pp. 177–190, 2017.
[113] Kolka, Z. Biolkova, V. and Biolek, D., “On hybrid emulation of memsys-
tems,” in Proceedings of the 2014 European Modelling Symposium. IEEE
Computer Society pp. 490–494, 2014.
[114] Kumngern, M. and Moungnoul, P., “A memristor emulator circuit based
on operational transconductance amplifiers,” Electrical Engineering/Elec-
tronics, Computer, Telecommunications and Information Technology (ECTI-
CON), 12th International Conference on. IEEE pp. 1–5, 2015.
[115] Hussein, A., Fouda, M. E., et al., “A simple mos realization of current con-
trolled memristor emulator,” in Microelectronics (ICM) 25th International
Conference on. IEEE pp.1–4, 2013.
[116] Yuce, E., “Floating inductance, FDNR and capacitance simulation circuit
employing only grounded passive elements,” International Journal of Elec-
tronics Vol. 93, pp. 679 – 688, 2006.
128
[117] Kumngern, M. and Moungnoul, P., “A memristor emulator circuit based
on operational transconductance amplifiers,” Electrical Engineering/Elec-
tronics, Computer, Telecommunications and Information Technology (ECTI-
CON), 12th International Conference on. IEEE pp. 1–5, 2015.
[118] Pershin, Y. V., and Ventra, M. Di, and Chua, L.O., “Circuit elements with
memory: memristors, memcapacitors and meminductors,”Proc. IEEE vol.
97, pp. 1717– 1724, 2009.
[119] Fitch, A. L. H, Iu, H. C, Wang, X. Y., Sreeram, V. and Qi, W. G., “Real-
ization of an analog model of memristor based on light dependent resistor,”
Proc. IEEE Int. Symp. Circuits Syst. pp. 1139–1142, Seoul, Korea, 2012.
[120] Goknar, I. C., Yildiz, M. and Minaei, S., “Metamutator Applications: a
Quadrature MOS only Oscillator and Transconductance/Transimpedance
Amplifiers,” Analog Integrated Circuits and Signal Processing vol. 89, no.
3, pp 801–808, 2016.
129