A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264
MetadataShow full item record
CitationFatemi, M. R. H., Ateş, H. F. & Salleh, R. (2009). A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264. Paper presented at the 2009 Innovative Technologies in Intelligent Systems and Industrial Applications, 1-4. doi:10.1109/CITISIA.2009.5224251
Bit-serial architectures offer a number of attractive features over their bit-parallel counterparts such as smaller area cost, lower density interconnection, a reduced number of pins, higher clock frequency, simpler routing and etc. These attractive features make them suitable for using in VLSI design and reduce overall production cost. In this paper, we propose the first least significant bit (LSB) bit-serial sum of absolute difference (SAD) hardware accelerator for integer variable block size motion estimation (VBSME) of H.264. This hardware accelerator is based on a previous state-of-art bit-parallel architecture namely propagate partial SAD. In order to reduce area cost and improve throughput, pixel truncation technique is adopted. Due to the bit-serial pipeline architecture and using small processing elements, our architecture works at much higher clock frequency (at least 4 times) and reduces area cost about 32% compared with its bit-parallel counterpart. The proposed hardware accelerator can be used in different disciplines from low bit rate to high bit rate by making a tradeoff between the degree of parallelism or using fast algorithm or a combination of both.
Source2009 Innovative Technologies in Intelligent Systems and Industrial Applications
Showing items related by title, author, creator and subject.
This paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation free algorithm that causes a high level reduction on memory requirement, hardware resources ...
This paper presents an accurate half-pixel variable block size motion estimation algorithm and its hardware architecture. The proposed algorithm does not require interpolation of the reference frame pixels and has near ...
Variable block-size motion estimation (VBSME) process occupies a major part of computation of an H.264 encoder, which is usually accelerated by bit-parallel hardware architectures with large I/O bit width to meet real-time ...