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A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC

dc.contributor.authorFatemi, Mohammad Reza Hosseinyen_US
dc.contributor.authorAteş, Hasan Fehmien_US
dc.contributor.authorSalleh, Rosli Binen_US
dc.date.accessioned2019-08-31T12:10:23Z
dc.date.accessioned2019-08-05T16:03:05Z
dc.date.available2019-08-31T12:10:23Z
dc.date.available2019-08-05T16:03:05Z
dc.date.issued2008
dc.identifier.citationFatemi, M. R. H., Ateş, H. F. & Salleh, R. (2008). A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC. Paper presented at the 818-821. doi:10.1109/IIH-MSP.2008.280en_US
dc.identifier.isbn9780769532783
dc.identifier.otherWOS:000258990400184
dc.identifier.urihttps://hdl.handle.net/11729/1803
dc.identifier.urihttps://dx.doi.org/10.1109/IIH-MSP.2008.280
dc.description.abstractThis paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation free algorithm that causes a high level reduction on memory requirement, hardware resources and computational complexity. A high performance, bit-serial pipeline architecture is proposed for quarter pixel accurate motion estimation which supports real-time H.264 encoding. Due to the bit-serial, modular and reusable architecture, it provides significant improvement in area cost (at least 390) and increases the macroblock processing speed almost 6 times when compared with the previous designs. The proposed architecture is suitable for portable multimedia devices where the memory and power consumption are limited.en_US
dc.language.isoengen_US
dc.publisherIEEE Computer Socen_US
dc.relation.isversionof10.1109/IIH-MSP.2008.280
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectArchitectureen_US
dc.subjectArea costsen_US
dc.subjectBit-serial architectureen_US
dc.subjectBit-serial pipeline architectureen_US
dc.subjectCalculatorsen_US
dc.subjectComputational complexityen_US
dc.subjectComputer architectureen_US
dc.subjectCopyingen_US
dc.subjectData storage equipmenten_US
dc.subjectDiamond searchen_US
dc.subjectEfficienten_US
dc.subjectEncodingen_US
dc.subjectEquationsen_US
dc.subjectH.264/AVCen_US
dc.subjectH.264/AVC encoderen_US
dc.subjectHardware resourcesen_US
dc.subjectHigh-performanceen_US
dc.subjectImage codingen_US
dc.subjectImage resolutionen_US
dc.subjectMacroblock processingen_US
dc.subjectMathematical modelen_US
dc.subjectMemory requirementen_US
dc.subjectMemory requirementsen_US
dc.subjectModularen_US
dc.subjectMotion estimationen_US
dc.subjectMotion Picture Experts Group standardsen_US
dc.subjectMultimedia devicesen_US
dc.subjectPipeline architecturesen_US
dc.subjectPipelinesen_US
dc.subjectPixelen_US
dc.subjectPixelsen_US
dc.subjectPortable multimedia devicesen_US
dc.subjectPower consumptionen_US
dc.subjectPower consumptionsen_US
dc.subjectProposed architecturesen_US
dc.subjectReusable architecturesen_US
dc.subjectSerial architecturesen_US
dc.subjectSignal processingen_US
dc.subjectSubpixel motion estimationen_US
dc.subjectSub-pixel motion estimationen_US
dc.subjectVideo codingen_US
dc.subjectVideo compressionen_US
dc.subjectVLSIen_US
dc.subjectVLSI architectureen_US
dc.subjectVlsi architecturesen_US
dc.titleA cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVCen_US
dc.typeconferenceObjecten_US
dc.description.versionPublisher's Versionen_US
dc.relation.journal2008 Fourth International Conference On Intelligent Information Hiding And Multimedia Signal Processing, Proceedingsen_US
dc.contributor.departmentIşık Üniversitesi, Mühendislik Fakültesi, Elektrik-Elektronik Mühendisliği Bölümüen_US
dc.contributor.departmentIşık University, Faculty of Engineering, Department of Electrical-Electronics Engineeringen_US
dc.contributor.authorID0000-0002-6842-1528
dc.identifier.startpage818
dc.identifier.endpage821
dc.peerreviewedYesen_US
dc.publicationstatusPublisheden_US
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.contributor.institutionauthorAteş, Hasan Fehmien_US


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