Front-end CMOS electronics for monolithic integration with CMUT arrays: Circuit design and initial experimental results

Abstract

This paper discusses design of CMOS-ASICs for monolithic integration of CMUT arrays by post-CMOS fabrication. We describe design strategies for monolithic integration and demonstrate the advantages of CMUT-on-CMOS approach. On the same wafer, separate sets of IC cells are designed to interface different types of CMUT arrays for IVUS and ICE applications. Circuit topologies include resistive feedback transimpedance amplifiers on the receiver side, along with multiplexers and buffers. Gains and bandwidths of receiving amplifiers are optimized separately to fit different array specifications such as number of elements, element size and operation bandwidth. To drive CMUTs a high voltage pulser array is designed in the same 3.3V unmodified CMOS technology by combining existing technological layers in an unconventional way. CMUT arrays are then built on top of the custom made 8" wafer containing these circuits fabricated in a 0.35µm standard CMOS process. We present initial characterization of the CMO electronics and pulse-echo measurements obtained post-CMOS fabricated CMUT elements.