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dc.contributor.authorFatemi, Mohammad Reza Hosseinyen_US
dc.contributor.authorAteş, Hasan Fehmien_US
dc.contributor.authorSalleh, Roslien_US
dc.date.accessioned2015-01-15T23:01:34Z
dc.date.available2015-01-15T23:01:34Z
dc.date.issued2010-12
dc.identifier.citationFATEMI, M. R. H., ATES, H. F., & SALLEH, R. (2010). FAST ALGORITHM ANALYSIS AND BIT-SERIAL ARCHITECTURE DESIGN FOR SUB-PIXEL MOTION ESTIMATION IN H.264. Journal of Circuits, Systems, and Computers, 19(8), 1665-1687. doi:10.1142/S0218126610006980en_US
dc.identifier.issn0218-1266
dc.identifier.issn1793-6454
dc.identifier.otherWOS:000285107500003
dc.identifier.urihttps://hdl.handle.net/11729/356
dc.identifier.urihttp://dx.doi.org/10.1142/S0218126610006980
dc.description.abstractThe sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. Due to the huge computational complexity and memory requirement of the H.264 SME, its hardware architecture design is an important issue especially in high resolution or low power applications. To solve the above difficulties, we propose several optimization techniques in both algorithm and architecture levels. In the algorithm level, we propose a parabolic based algorithm for SME with quarter-pixel accuracy which reduces the computational budget by 94.35% and the memory access requirement by 98.5% in comparison to the standard interpolate and search method. In addition, a fast version of the proposed algorithm is presented that reduces the computational budget 46.28% further while maintaining the video quality. In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. Also, several optimization techniques including the sum of absolute differences truncation, source sharing exploiting and power saving techniques are applied to the proposed architecture which reduce power consumption and area. Our design can save between 57.71-90.01% of area cost and improves the macroblock (MB) processing speed between 1.7-8.44 times when compared to previous designs. Implementation results show that our design can support real time HD1080 format with 20.3 k gate counts at the operation frequency of 144.9 MHz.en_US
dc.language.isoengen_US
dc.publisherWorld Scientific Publishing Companyen_US
dc.relation.isversionof10.1142/S0218126610006980
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.sourceJournal of circuits, systems, and computersen_US
dc.subjectVideo compressionen_US
dc.subjectSub-pixel motion estimationen_US
dc.subjectH.264 standarden_US
dc.subjectBit-serial architectureen_US
dc.subjectVlsi architectureen_US
dc.subjectEncoderen_US
dc.subjectReuseen_US
dc.titleFast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264en_US
dc.typearticleen_US
dc.description.versionPublisher's versionen_US
dc.contributor.departmentIşık Üniversitesi, Mühendislik Fakültesi, Elektrik-Elektronik Mühendisliği Bölümüen_US
dc.contributor.departmentIşık University, Faculty of Engineering, Department of Electrical-Electronics Engineeringen_US
dc.contributor.authorIDTR17416
dc.identifier.volume19
dc.identifier.issue8
dc.identifier.startpage1665
dc.identifier.endpage1687
dc.peerreviewedYesen_US
dc.publicationstatusPublisheden_US
dc.relation.publicationcategoryBelirsizen_US
dc.contributor.institutionauthorAteş, Hasan Fehmi


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