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Yayın 3-D Mesh geometry compression with set partitioning in the spectral domain(IEEE-INST Electrical Electronics Engineers Inc, 2010-02) Bayazıt, Uluğ; Konur, Umut; Ateş, Hasan FehmiThis paper explains the development of a highly efficient progressive 3-D mesh geometry coder based on the region adaptive transform in the spectral mesh compression method. A hierarchical set partitioning technique, originally proposed for the efficient compression of wavelet transform coefficients in high-performance wavelet-based image coding methods, is proposed for the efficient compression of the coefficients of this transform. Experiments confirm that the proposed coder employing such a region adaptive transform has a high compression performance rarely achieved by other state of the art 3-D mesh geometry compression algorithms. A new, high-performance fixed spectral basis method is also proposed for reducing the computational complexity of the transform. Many-to-one mappings are employed to relate the coded irregular mesh region to a regular mesh whose basis is used. To prevent loss of compression performance due to the low-pass nature of such mappings, transitions are made from transform-based coding to spatial coding on a per region basis at high coding rates. Experimental results show the performance advantage of the newly proposed fixed spectral basis method over the original fixed spectral basis method in the literature that employs one-to-one mappings.Yayın H.264 video kodlamada B-çerçeveler için kodçözücü tarafında aday devinim vektör seçimi(IEEE, 2012-04-18) Ateş, Hasan Fehmi; Gaurav, RahulH.264 standardında devinim vektör farklarının kodlanması sebebiyle özellikle düşük bit hızlarında nesne sınırlarında devinimdeki ani değişiklikler harcanan bit miktarlarını artırmaktadır. Bu bildiride B-çerçevelerde kod çözücü desteği ile verimli devinim vektör kodlama için özgün bir yöntem sunulmuştur. Bu yöntemde kod çözücü gerçek devinim kestirimi kullanarak az sayıda aday vektör içeren bir vektör kümesi belirler. Devinim kestirim doğrulu günün iyileştirilmesi amacıyla bu aday vektörler etrafında kısıtlı bir arama yapılır. Bu aramaya en iyi olma ihtimali düşük vektörler dahil edilmeleyerek aday vektor alt-kümesinin küçük tutulması sağlanır. Sonuç¸ta her makroblok için aday vektör kümeleri kod çözücü tarafından belirlendiği için, belirtik bir şekilde devinim bilgisinin kodlanmasına gerek kalmamakta ve bu da kodlama için gerekli bit hızını düşürmektedir. Algoritmanın aynı bit hızlarında referans H.264 sonuçlarına göre 0.39 dB PSNR kazancı sağladığı gösterilmiştir. Ayrıca sıkıştırılmış B-çerçevelerin görsel kalitesinde kayda değer bir iyileşme gözlenmistir.Yayın Wavelet-based image compression by hierarchical quantization indexing(IEEE, 2009) Ateş, Hasan Fehmi; Tamer, EnginIn this paper, we introduce the quantization index hierarchy, which is used for efficient coding of quantized wavelet coefficients. A hierarchical classification map is defined in each wavelet subband, which describes the quantized data through a series of index classes. Going from bottom to the top of the tree, neighboring coefficients are combined to form classes that represent some statistics of the quantization indices of these coefficients. Higher levels of the tree are constructed iteratively by repeating this class assignment to partition the coefficients into larger subsets. The class assignments are optimized using a rate-distortion cost analysis. The optimized tree is coded hierarchically from top to bottom by coding the class membership information at each level of the tree. Despite its simplicity, the algorithm produces PSNR results that are competitive with the state-of-art coders in literature.Yayın A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264(IEEE, 2009) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinBit-serial architectures offer a number of attractive features over their bit-parallel counterparts such as smaller area cost, lower density interconnection, a reduced number of pins, higher clock frequency, simpler routing and etc. These attractive features make them suitable for using in VLSI design and reduce overall production cost. In this paper, we propose the first least significant bit (LSB) bit-serial sum of absolute difference (SAD) hardware accelerator for integer variable block size motion estimation (VBSME) of H.264. This hardware accelerator is based on a previous state-of-art bit-parallel architecture namely propagate partial SAD. In order to reduce area cost and improve throughput, pixel truncation technique is adopted. Due to the bit-serial pipeline architecture and using small processing elements, our architecture works at much higher clock frequency (at least 4 times) and reduces area cost about 32% compared with its bit-parallel counterpart. The proposed hardware accelerator can be used in different disciplines from low bit rate to high bit rate by making a tradeoff between the degree of parallelism or using fast algorithm or a combination of both.
