Filtreler

2007 - 200912010 - 20131
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Ayarlar

Yazar: Ateş, Hasan Fehmi × Konu: Interpolation ×

Arama Sonuçları

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  • Küçük Resim
    Yayın
    Decoder-side super-resolution and frame interpolation for improved H.264 video coding
    (IEEE, 2013) Ateş, Hasan Fehmi
    In literature decoder-side motion estimation is shown to improve video coding efficiency of both H.264 and HEVC standards. In this paper we introduce enhanced skip and direct modes for H.264 coding using decoder-side super-resolution (SR) and frame interpolation. P-and B-frames are downsampled and H.264 encoded at lower resolution (LR). Then reconstructed LR frames are super-resolved using decoder-side motion estimation. Alternatively for B-frames, bidirectional true motion estimation is performed to synthesize a B-frame from its reference frames. For P-frames, bicubic interpolation of the LR frame is used as an alternative to SR reconstruction. A rate-distortion optimal mode selection algorithm determines for each MB which of the two reconstructions to use as skip/direct mode prediction. Simulations indicate an average of 1.04 dB PSNR improvement or 23.0% bitrate reduction at low bitrates when compared to H.264 standard. Average PSNR gains reach as high as 3.95 dB depending on the video content and frame rate.
  • Küçük Resim
    Yayın
    An algorithm and its architecture for half-pixel variable block size motion estimation
    (IEEE, 2007) Fatemi, Mohammad Reza Hosseiny; Salleh, Rosli Bin; Ateş, Hasan Fehmi
    This paper presents an accurate half-pixel variable block size motion estimation algorithm and its hardware architecture. The proposed algorithm does not require interpolation of the reference frame pixels and has near performance to the conventional interpolation-search methods. These simplifications cause high level reduction in computational time and gate count without the need for internal or external half-pixel accuracy search memory. A simple, low latency, high throughput and fully utilized pipelined architecture of proposed algorithm is implemented in VHDL The proposed hardware architecture uses shift registers for multiplication and pipelining technique and can support half-pixel accuracy variable block size motion estimation for the real time HDTV format (1920 x1280 resolution and 30 Frames/sec).