Filtreler

2009 - 200912010 - 20191
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Bölüm: Işık University, Faculty of Engineering, Department of Electrical-Electronics Engineering × Konu: Intelligent systems ×

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  • Küçük Resim
    Yayın
    ViLDAR-Visible light sensing-based speed estimation using vehicle headlamps
    (IEEE, 2019-11) Abuella, Hisham; Miramirkhani, Farshad; Ekin, Sabit; Uysal, Murat; Ahmed, Samir
    The introduction of light emitting diodes (LED) in automotive exterior lighting systems provides opportunities to develop viable alternatives to conventional communication and sensing technologies. Most of the advanced driver-assist and autonomous vehicle technologies are based on Radio Detection and Ranging (RADAR) or Light Detection and Ranging (LiDAR) systems that use radio frequency or laser signals, respectively. While reliable and real-time information on vehicle speeds is critical for traffic operations management and autonomous vehicles safety, RADAR or LiDAR systems have some deficiencies especially in curved road scenarios where the incidence angle is rapidly varying. In this paper, we propose a novel speed estimation system so-called the Visible Light Detection and Ranging (ViLDAR) that builds upon sensing visible light variation of the vehicle's headlamp. We determine the accuracy of the proposed speed estimator in straight and curved road scenarios. We further present how the algorithm design parameters and the channel noise level affect the speed estimation accuracy. For wide incidence angles, the simulation results show that the ViLDAR outperforms RADAR/LiDAR systems in both straight and curved road scenarios.
  • Küçük Resim
    Yayın
    A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264
    (IEEE, 2009) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli Bin
    Bit-serial architectures offer a number of attractive features over their bit-parallel counterparts such as smaller area cost, lower density interconnection, a reduced number of pins, higher clock frequency, simpler routing and etc. These attractive features make them suitable for using in VLSI design and reduce overall production cost. In this paper, we propose the first least significant bit (LSB) bit-serial sum of absolute difference (SAD) hardware accelerator for integer variable block size motion estimation (VBSME) of H.264. This hardware accelerator is based on a previous state-of-art bit-parallel architecture namely propagate partial SAD. In order to reduce area cost and improve throughput, pixel truncation technique is adopted. Due to the bit-serial pipeline architecture and using small processing elements, our architecture works at much higher clock frequency (at least 4 times) and reduces area cost about 32% compared with its bit-parallel counterpart. The proposed hardware accelerator can be used in different disciplines from low bit rate to high bit rate by making a tradeoff between the degree of parallelism or using fast algorithm or a combination of both.