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Yayın Low complexity least minimum symbol error rate based post-distortion for vehicular VLC(Institute of Electrical and Electronics Engineers Inc., 2020-10-22) Mitra, Rangeet; Miramirkhani, Farshad; Bhatia, Vimal; Uysal, MuratVehicular visible light communications (VLC) has emerged as a viable supplement for high speed next-generation vehicle to vehicle (V2V) communication systems. However, performance of a V2V-VLC link is impaired due to nonlinear transfer-characteristics of light emitting diodes (LEDs), and inter-symbol interference (ISI). In this article, a low-complexity least-squares based post-distortion algorithm is formulated over reproducing kernel Hilbert space (RKHS) for a multi-hop V2V-VLC link. The impairments encountered in V2V-VLC channels are mitigated in RKHS by a minimum symbol error-rate post-distorter using a low dimensional approximation of random Fourier features (RFF) (which is a soft approximation of the feature-map to RKHS), that facilitates computationally simple post-distortion under finite memory-budget. The convergence and the BER-performance of the proposed post-distorter is analyzed over realistic V2V VLC channels obtained via ray-tracing. From the analysis, and the presented computer-simulations, the proposed post-distorter is found to exhibit equivalent convergence characteristics and error-rate over reasonable distances, with much lower computational complexity.Yayın Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264(World Scientific Publishing Company, 2010-12) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinThe sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. Due to the huge computational complexity and memory requirement of the H.264 SME, its hardware architecture design is an important issue especially in high resolution or low power applications. To solve the above difficulties, we propose several optimization techniques in both algorithm and architecture levels. In the algorithm level, we propose a parabolic based algorithm for SME with quarter-pixel accuracy which reduces the computational budget by 94.35% and the memory access requirement by 98.5% in comparison to the standard interpolate and search method. In addition, a fast version of the proposed algorithm is presented that reduces the computational budget 46.28% further while maintaining the video quality. In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. Also, several optimization techniques including the sum of absolute differences truncation, source sharing exploiting and power saving techniques are applied to the proposed architecture which reduce power consumption and area. Our design can save between 57.71-90.01% of area cost and improves the macroblock (MB) processing speed between 1.7-8.44 times when compared to previous designs. Implementation results show that our design can support real time HD1080 format with 20.3 k gate counts at the operation frequency of 144.9 MHz.
