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Yayın Decoder-side super-resolution and frame interpolation for improved H.264 video coding(IEEE, 2013) Ateş, Hasan FehmiIn literature decoder-side motion estimation is shown to improve video coding efficiency of both H.264 and HEVC standards. In this paper we introduce enhanced skip and direct modes for H.264 coding using decoder-side super-resolution (SR) and frame interpolation. P-and B-frames are downsampled and H.264 encoded at lower resolution (LR). Then reconstructed LR frames are super-resolved using decoder-side motion estimation. Alternatively for B-frames, bidirectional true motion estimation is performed to synthesize a B-frame from its reference frames. For P-frames, bicubic interpolation of the LR frame is used as an alternative to SR reconstruction. A rate-distortion optimal mode selection algorithm determines for each MB which of the two reconstructions to use as skip/direct mode prediction. Simulations indicate an average of 1.04 dB PSNR improvement or 23.0% bitrate reduction at low bitrates when compared to H.264 standard. Average PSNR gains reach as high as 3.95 dB depending on the video content and frame rate.Yayın Rate-distortion and complexity joint optimization for fast motion estimation in H.264 video coding(IEEE, 2006) Ateş, Hasan Fehmi; Kanberoğlu, Berkay; Altunbaşak, YücelH.264 video coding standard offers several coding modes including inter-prediction modes that use macroblock partitions with variable block sizes. Choosing a rate-distortion optimal mode among these possibilities contributes significantly to the superior coding efficiency of the H.264 encoder. Unfortunately, searching for optimal motion vectors of each possible subblock incurs a heavy computational cost. In this paper, in order to reduce the complexity of integer-pel motion estimation, we propose a rate-distortion and complexity joint optimization method that selects for each MB a subset of partitions to evaluate during motion estimation. This selection is based on simple measures of spatio-temporal activity within the MB. The procedure is optimized to minimize mode estimation error at a certain level of computational complexity. Simulation results show that the algorithm speeds up the motion estimation module by a factor of up to 20 with little loss in coding efficiency.Yayın Low complexity inter-mode selection for H.264(IEEE, 2006) Ba, Seydou Nourou; Altunbaşak, Yücel; Ateş, Hasan FehmiThe coding efficiency of the H.264/AVC standard enables the transmission of high quality video over bandwidth limited networks. Due to the use of multiple Macroblock (MB) partitions, the Motion estimation module has extremely high complexity that makes it unpractical for most real-time applications on resource-limited platforms such as hand held devices. In this paper we propose a novel algorithm that significantly reduces the encoding complexity while maintaining high rate distortion performance. The proposed method reduces the Motion estimation (ME) computational complexity by accurately predicting the optimal MB partitions and restricting the number of candidate modes based on a-priori probabilities computed from spatio-temporal information. The experimental results show that the speed up of UmHexagonS [1] (one of the most efficient ME algorithms) can be doubled while maintaining the coding efficiency of Full Search.Yayın Decoder side true motion estimation for very low bitrate b-frame coding(IEEE, 2011) Ateş, Hasan Fehmi; Çizmeci, BurakIn H.264 standard, coding of motion vectors constitutes a significant portion of total bitrate especially at low bitrate regimes. This is because differential coding of motion vectors is inefficient when the bit budget is very low. In this paper, we propose a novel estimation and coding algorithm for motion vectors of B-frames at very low bitrates. In this method, the encoder selects the optimal motion vector from a limited set of candidate vectors that are determined at the decoder side using true motion estimation. Since these candidate vector sets are fixed by the decoder for each macroblock, there is no need for explicit coding of motion information, which reduces the bitrate required for coding. Also, true motion vector estimates are used for improved direct mode coding in B-frames. The algorithm provides an average of 0.68 dB PSNR gain for B-frames when compared to the reference H.264 results at the same bitrates. Simulation results also indicate significant improvement in visual quality of the compressed B-frames.Yayın Fast inter-mode decision and selective quarter-pel refinement in H.264 video coding(IEEE, 2008) Ateş, Hasan FehmiIn H.264 video coding standard, there exist several inter - prediction modes that use macroblock partitions with variable block sizes. Choosing a rate-distortion optimal coding mode for each macroblock is essential for the best possible coding performance, but also prohibitive due to the heavy computational complexity associated with the required rate-distortion calculations. Likewise, sub-pel motion refinement improves the coding efficiency, but becomes a major computational bottleneck when integer-pel search is executed fast. In this paper, we present a simple strategy to reduce the complexity of quarter-pel refinement and inter-mode decision with minimum loss of coding efficiency. Based on the results of the half-pel motion estimation step, our method evaluates the likelihood of each inter-coding mode being optimal. Then, quarter-pel refinement and actual rate and distortion are computed for only those coding modes with sufficient chance of being optimal. We claim that this method minimizes optimal mode estimation error at a given level of refinement and mode decision complexity. Simulation results show that the algorithm speeds up quarter-pel search and inter-mode selection modules by a factor of about 6 with less than 0.12 dB PSNR loss.Yayın Occlusion aware motion compensation for video frame rate up-conversion(2010) Çizmeci, Burak; Ateş, Hasan FehmiSince the emergence of high definition (HD) display technologies, video standards conversion problem has become an important issue in storage, transmission and display of video content. Video frame rate up-conversion (FRUC) is considered as a standard task for today's HD displays because these displays reach high refresh rates of at least 100/120 Hz and low video frame rates should be pulled up by a factor of 2 or more before display. Motion compensated FRUC techniques are proposed to avoid motion blur and motion judder at high refresh rates, but these techniques suffer from spatial inconsistencies and artifacts especially in occluded regions of the interpolated frames. This paper introduces a new video FRUC method that aims to remove both motion judder and occlusion artifacts and generate smooth object motion for high quality displays. An occlusion adaptive overlapped block motion compensation (OBMC) technique is proposed, which provides spatio-temporally consistent frame interpolation. Covered/uncovered regions are detected by analyzing the discontinuities of the motion vector field. The occlusion regions are interpolated using this covered/uncovered decision and a new error metric that measures spatial consistency. Compared to existing methods, the proposed algorithm achieves FRUC with fewer artifacts and better spatial resolution especially in occluded areas.Yayın An algorithm and its architecture for half-pixel variable block size motion estimation(IEEE, 2007) Fatemi, Mohammad Reza Hosseiny; Salleh, Rosli Bin; Ateş, Hasan FehmiThis paper presents an accurate half-pixel variable block size motion estimation algorithm and its hardware architecture. The proposed algorithm does not require interpolation of the reference frame pixels and has near performance to the conventional interpolation-search methods. These simplifications cause high level reduction in computational time and gate count without the need for internal or external half-pixel accuracy search memory. A simple, low latency, high throughput and fully utilized pipelined architecture of proposed algorithm is implemented in VHDL The proposed hardware architecture uses shift registers for multiplication and pipelining technique and can support half-pixel accuracy variable block size motion estimation for the real time HDTV format (1920 x1280 resolution and 30 Frames/sec).Yayın A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC(IEEE Computer Soc, 2008) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinThis paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation free algorithm that causes a high level reduction on memory requirement, hardware resources and computational complexity. A high performance, bit-serial pipeline architecture is proposed for quarter pixel accurate motion estimation which supports real-time H.264 encoding. Due to the bit-serial, modular and reusable architecture, it provides significant improvement in area cost (at least 390) and increases the macroblock processing speed almost 6 times when compared with the previous designs. The proposed architecture is suitable for portable multimedia devices where the memory and power consumption are limited.Yayın Analysis and design of low-cost bit-serial architectures for motion estimation in H.264/AVC(Springer, 2013-05) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinVariable block-size motion estimation (VBSME) process occupies a major part of computation of an H.264 encoder, which is usually accelerated by bit-parallel hardware architectures with large I/O bit width to meet real-time constrains. However, such kind of architectures increase the area overhead and pin count, and therefore will not be suitable for area-constrained electronic consumer designs such as small portable multimedia devices. This paper addresses this problem by proposing two area efficient least significant bit (LSB) bit-serial architectures with small pin numbers. Both designs take advantage of data reusing technique in different ways for sum of absolute differences (SAD) computation and reading reference pixels, leading to a considerable reduction of memory bandwidth. The first architecture propagates the partial SAD and sum results and broadcasts the reference pixel rows whereas the second design reuse the SAD of small blocks and has a reconfigurable reference buffer leading to a better memory bandwidth when using hardware parallelism. The proposed designs benefit from several optimization techniques including an efficient serial absolute difference architecture, word length reduction by parallelism, bit truncation, mode filtering, and macroblock (MB) level subsampling, which significantly enhance their performances in terms of silicon area, throughput, latency, and power consumption. The first and second designs can support full search VBSME of 720 x 480 video with 30 frames per second (fps), two reference frames, and [-16, 15] search range at a clock frequency of 414 MHz with 29.28 k and 31.5 k gates, respectively.Yayın Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264(World Scientific Publishing Company, 2010-12) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinThe sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. Due to the huge computational complexity and memory requirement of the H.264 SME, its hardware architecture design is an important issue especially in high resolution or low power applications. To solve the above difficulties, we propose several optimization techniques in both algorithm and architecture levels. In the algorithm level, we propose a parabolic based algorithm for SME with quarter-pixel accuracy which reduces the computational budget by 94.35% and the memory access requirement by 98.5% in comparison to the standard interpolate and search method. In addition, a fast version of the proposed algorithm is presented that reduces the computational budget 46.28% further while maintaining the video quality. In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. Also, several optimization techniques including the sum of absolute differences truncation, source sharing exploiting and power saving techniques are applied to the proposed architecture which reduce power consumption and area. Our design can save between 57.71-90.01% of area cost and improves the macroblock (MB) processing speed between 1.7-8.44 times when compared to previous designs. Implementation results show that our design can support real time HD1080 format with 20.3 k gate counts at the operation frequency of 144.9 MHz.
