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Yayın A path loss model for link budget analysis of indoor visible light communications(Istanbul Univ-Cerrahpasa, 2021-05) Miramirkhani, FarshadIn the context of beyond 5G indoor communication systems, visible light communications (VLC) has emerged as a viable supplement for existing radio frequency based systems and as an enabler for high data rate communications. However, the existing indoor VLC systems are limited by detrimental outages caused by fluctuations in the VLC channel gain because of user mobility. In this study, we proposed a tractable path loss model for indoor VLC that reflects the effect of room size and coating material of surfaces. We performed an extensive advanced ray tracing simulation to obtain the channel impulse responses within a room and presented a path loss model as a function of distance, room size, and coating material through curve fitting. In addition, path loss parameters such as the path loss exponent and the standard deviation of the shadowing component were determined. The simulation results indicate that path loss is a linear function of distance, path loss exponent is a function of room size and coating material, and shadowing follows a log normal distribution.Yayın Fast algorithm analysis and bit-serial architecture design for sub-pixel motion estimation in H.264(World Scientific Publishing Company, 2010-12) Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli BinThe sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. Due to the huge computational complexity and memory requirement of the H.264 SME, its hardware architecture design is an important issue especially in high resolution or low power applications. To solve the above difficulties, we propose several optimization techniques in both algorithm and architecture levels. In the algorithm level, we propose a parabolic based algorithm for SME with quarter-pixel accuracy which reduces the computational budget by 94.35% and the memory access requirement by 98.5% in comparison to the standard interpolate and search method. In addition, a fast version of the proposed algorithm is presented that reduces the computational budget 46.28% further while maintaining the video quality. In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. Also, several optimization techniques including the sum of absolute differences truncation, source sharing exploiting and power saving techniques are applied to the proposed architecture which reduce power consumption and area. Our design can save between 57.71-90.01% of area cost and improves the macroblock (MB) processing speed between 1.7-8.44 times when compared to previous designs. Implementation results show that our design can support real time HD1080 format with 20.3 k gate counts at the operation frequency of 144.9 MHz.
