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Toplam kayıt 9, listelenen: 1-9
H.264 video kodlamada çerçeve seviyesinde karmaşıklık kontrolü
(IEEE, 2007)
H.264 kodlama standardı, değişken blok boyutlu makroblok bölüntüleri kullanan çok sayıda farklı çerçeveler arası kestirim kipini desteklemektedir. Ne var ki, her olası bölüntü için eniyi devinim vektörlerini aramanın ...
Rate-distortion and complexity joint optimization for fast motion estimation in H.264 video coding
(IEEE, 2006)
H.264 video coding standard offers several coding modes including inter-prediction modes that use macroblock partitions with variable block sizes. Choosing a rate-distortion optimal mode among these possibilities contributes ...
Fast inter-mode decision and selective quarter-pel refinement in H.264 video coding
(IEEE, 2008)
In H.264 video coding standard, there exist several inter - prediction modes that use macroblock partitions with variable block sizes. Choosing a rate-distortion optimal coding mode for each macroblock is essential for the ...
Decoder side true motion estimation for very low bitrate b-frame coding
(IEEE, 2011)
In H.264 standard, coding of motion vectors constitutes a significant portion of total bitrate especially at low bitrate regimes. This is because differential coding of motion vectors is inefficient when the bit budget is ...
H.264 standardı için süper-çözünürlük tabanlı kodlama yaklaşımı
(IEEE, 2013-04-26)
Kodçözücü tarafında süper-çözünürlük (SC) uygulayarak H.264 standardının video kodlama verimliliğinin iyileştirilmesi literatürde ele alınmıştır. Bu bildiride farklı olarak, SC¸ kestirimi kodlama sırasında H.264 standardının ...
A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264
(IEEE, 2009)
Bit-serial architectures offer a number of attractive features over their bit-parallel counterparts such as smaller area cost, lower density interconnection, a reduced number of pins, higher clock frequency, simpler routing ...
A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC
(IEEE Computer Soc, 2008)
This paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation free algorithm that causes a high level reduction on memory requirement, hardware resources ...
An algorithm and its architecture for half-pixel variable block size motion estimation
(IEEE, 2007)
This paper presents an accurate half-pixel variable block size motion estimation algorithm and its hardware architecture. The proposed algorithm does not require interpolation of the reference frame pixels and has near ...
Low complexity inter-mode selection for H.264
(IEEE, 2006)
The coding efficiency of the H.264/AVC standard enables the transmission of high quality video over bandwidth limited networks. Due to the use of multiple Macroblock (MB) partitions, the Motion estimation module has extremely ...