A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC
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CitationFatemi, M. R. H., Ateş, H. F. & Salleh, R. (2008). A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC. Paper presented at the 818-821. doi:10.1109/IIH-MSP.2008.280
This paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation free algorithm that causes a high level reduction on memory requirement, hardware resources and computational complexity. A high performance, bit-serial pipeline architecture is proposed for quarter pixel accurate motion estimation which supports real-time H.264 encoding. Due to the bit-serial, modular and reusable architecture, it provides significant improvement in area cost (at least 390) and increases the macroblock processing speed almost 6 times when compared with the previous designs. The proposed architecture is suitable for portable multimedia devices where the memory and power consumption are limited.
Source2008 Fourth International Conference On Intelligent Information Hiding And Multimedia Signal Processing, Proceedings
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