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  • Mühendislik Fakültesi / Faculty of Engineering
  • Elektrik-Elektronik Mühendisliği Bölümü / Department of Electrical-Electronics Engineering
  • MF - Bildiri Koleksiyonu | Elektrik-Elektronik Mühendisliği Bölümü / Department of Electrical-Electronics Engineering
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  •   DSpace@Işık
  • 1- Fakülteler | Faculties
  • Mühendislik Fakültesi / Faculty of Engineering
  • Elektrik-Elektronik Mühendisliği Bölümü / Department of Electrical-Electronics Engineering
  • MF - Bildiri Koleksiyonu | Elektrik-Elektronik Mühendisliği Bölümü / Department of Electrical-Electronics Engineering
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A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC

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Date

2008

Author

Fatemi, Mohammad Reza Hosseiny
Ateş, Hasan Fehmi
Salleh, Rosli Bin

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Citation

Fatemi, M. R. H., Ateş, H. F. & Salleh, R. (2008). A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC. Paper presented at the 818-821. doi:10.1109/IIH-MSP.2008.280

Abstract

This paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation free algorithm that causes a high level reduction on memory requirement, hardware resources and computational complexity. A high performance, bit-serial pipeline architecture is proposed for quarter pixel accurate motion estimation which supports real-time H.264 encoding. Due to the bit-serial, modular and reusable architecture, it provides significant improvement in area cost (at least 390) and increases the macroblock processing speed almost 6 times when compared with the previous designs. The proposed architecture is suitable for portable multimedia devices where the memory and power consumption are limited.

Source

2008 Fourth International Conference On Intelligent Information Hiding And Multimedia Signal Processing, Proceedings

URI

https://hdl.handle.net/11729/1803
https://dx.doi.org/10.1109/IIH-MSP.2008.280

Collections

  • MF - Bildiri Koleksiyonu | Elektrik-Elektronik Mühendisliği Bölümü / Department of Electrical-Electronics Engineering [223]
  • Scopus İndeksli Bildiri Koleksiyonu [458]
  • WoS İndeksli Bildiri Koleksiyonu [356]

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  • An algorithm and its architecture for half-pixel variable block size motion estimation 

    Fatemi, Mohammad Reza Hosseiny; Salleh, Rosli Bin; Ateş, Hasan Fehmi (IEEE, 2007)
    This paper presents an accurate half-pixel variable block size motion estimation algorithm and its hardware architecture. The proposed algorithm does not require interpolation of the reference frame pixels and has near ...
  • A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264 

    Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli Bin (IEEE, 2009)
    Bit-serial architectures offer a number of attractive features over their bit-parallel counterparts such as smaller area cost, lower density interconnection, a reduced number of pins, higher clock frequency, simpler routing ...
  • Analysis and design of low-cost bit-serial architectures for motion estimation in H.264/AVC 

    Fatemi, Mohammad Reza Hosseiny; Ateş, Hasan Fehmi; Salleh, Rosli Bin (Springer, 2013-05)
    Variable block-size motion estimation (VBSME) process occupies a major part of computation of an H.264 encoder, which is usually accelerated by bit-parallel hardware architectures with large I/O bit width to meet real-time ...



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