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Toplam kayıt 3, listelenen: 1-3
A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264
(IEEE, 2009)
Bit-serial architectures offer a number of attractive features over their bit-parallel counterparts such as smaller area cost, lower density interconnection, a reduced number of pins, higher clock frequency, simpler routing ...
A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC
(IEEE Computer Soc, 2008)
This paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation free algorithm that causes a high level reduction on memory requirement, hardware resources ...
An algorithm and its architecture for half-pixel variable block size motion estimation
(IEEE, 2007)
This paper presents an accurate half-pixel variable block size motion estimation algorithm and its hardware architecture. The proposed algorithm does not require interpolation of the reference frame pixels and has near ...