Ara
Toplam kayıt 16, listelenen: 11-16
A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264
(IEEE, 2009)
Bit-serial architectures offer a number of attractive features over their bit-parallel counterparts such as smaller area cost, lower density interconnection, a reduced number of pins, higher clock frequency, simpler routing ...
A cost-efficient bit-serial architecture for sub-pixel motion estimation of H.264/AVC
(IEEE Computer Soc, 2008)
This paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation free algorithm that causes a high level reduction on memory requirement, hardware resources ...
An algorithm and its architecture for half-pixel variable block size motion estimation
(IEEE, 2007)
This paper presents an accurate half-pixel variable block size motion estimation algorithm and its hardware architecture. The proposed algorithm does not require interpolation of the reference frame pixels and has near ...
Low complexity inter-mode selection for H.264
(IEEE, 2006)
The coding efficiency of the H.264/AVC standard enables the transmission of high quality video over bandwidth limited networks. Due to the use of multiple Macroblock (MB) partitions, the Motion estimation module has extremely ...
Occlusion aware motion compensation for video frame rate up-conversion
(2010)
Since the emergence of high definition (HD) display technologies, video standards conversion problem has become an important issue in storage, transmission and display of video content. Video frame rate up-conversion (FRUC) ...
Kodlayıcı destekli video çerçeve hız artırımı
(IEEE, 2011)
Videoda çerçeve hız artırımı (ÇHA), devinim denkleştirme yöntemlerinin kullanılmasıyla hareketlerin daha keskin ve sürekli gösterimini sağlayarak görsel kaliteyi artırmaktadır. Fakat, devinim kestiriminde karşılaşılan ...